case 0x3A:
switch (dpmac_id) {
case 1:
- wriop_set_phy_address(dpmac_id, riser_phy_addr[1]);
+ wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[1]);
break;
case 2:
- wriop_set_phy_address(dpmac_id, riser_phy_addr[0]);
+ wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[0]);
break;
case 3:
- wriop_set_phy_address(dpmac_id, riser_phy_addr[3]);
+ wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[3]);
break;
case 7:
- wriop_set_phy_address(dpmac_id, riser_phy_addr[2]);
+ wriop_set_phy_address(dpmac_id, 0, riser_phy_addr[2]);
break;
default:
printf("WRIOP: Wrong DPMAC%d set to SGMII", dpmac_id);
case 4:
case 5:
case 6:
- wriop_set_phy_address(dpmac_id, dpmac_id + 9);
+ wriop_set_phy_address(dpmac_id, 0, dpmac_id + 9);
break;
case 7:
case 8:
case 9:
case 10:
- wriop_set_phy_address(dpmac_id, dpmac_id + 1);
+ wriop_set_phy_address(dpmac_id, 0, dpmac_id + 1);
break;
}
case 0x15:
case 0x1D:
case 0x1E:
- wriop_set_phy_address(i, i + 26);
+ wriop_set_phy_address(i, 0, i + 26);
ls1088a_qds_enable_SFP_TX(SFP_TX);
break;
default:
switch (dpmac_id) {
case 4:
- wriop_set_phy_address(dpmac_id, RGMII_PHY1_ADDR);
+ wriop_set_phy_address(dpmac_id, 0, RGMII_PHY1_ADDR);
dpmac_info[dpmac_id].board_mux = EMI1_RGMII1;
bus = mii_dev_for_muxval(EMI1_RGMII1);
wriop_set_mdio(dpmac_id, bus);
break;
case 5:
- wriop_set_phy_address(dpmac_id, RGMII_PHY2_ADDR);
+ wriop_set_phy_address(dpmac_id, 0, RGMII_PHY2_ADDR);
dpmac_info[dpmac_id].board_mux = EMI1_RGMII2;
bus = mii_dev_for_muxval(EMI1_RGMII2);
wriop_set_mdio(dpmac_id, bus);
* a MAC has no PHY address, we give a PHY address to XFI
* MAC error.
*/
- wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a);
- wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR);
- wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a);
+ wriop_set_phy_address(WRIOP1_DPMAC2, 0, AQ_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC3, 0, QSGMII1_PORT1_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC4, 0, QSGMII1_PORT2_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC5, 0, QSGMII1_PORT3_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC6, 0, QSGMII1_PORT4_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC7, 0, QSGMII2_PORT1_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC8, 0, QSGMII2_PORT2_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC9, 0, QSGMII2_PORT3_PHY_ADDR);
+ wriop_set_phy_address(WRIOP1_DPMAC10, 0,
+ QSGMII2_PORT4_PHY_ADDR);
break;
default:
switch (++slot) {
case 1:
/* Slot housing a SGMII riser card? */
- wriop_set_phy_address(dpmac_id,
+ wriop_set_phy_address(dpmac_id, 0,
riser_phy_addr[dpmac_id - 1]);
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
bus = mii_dev_for_muxval(EMI1_SLOT1);
break;
case 2:
/* Slot housing a SGMII riser card? */
- wriop_set_phy_address(dpmac_id,
+ wriop_set_phy_address(dpmac_id, 0,
riser_phy_addr[dpmac_id - 1]);
dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
bus = mii_dev_for_muxval(EMI1_SLOT2);
if (slot == EMI_NONE)
return;
if (serdes1_prtcl == 0x39) {
- wriop_set_phy_address(dpmac_id,
+ wriop_set_phy_address(dpmac_id, 0,
riser_phy_addr[dpmac_id - 2]);
if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
env_hwconfig))
- wriop_set_phy_address(dpmac_id,
+ wriop_set_phy_address(dpmac_id, 0,
riser_phy_addr[dpmac_id - 3]);
} else {
- wriop_set_phy_address(dpmac_id,
+ wriop_set_phy_address(dpmac_id, 0,
riser_phy_addr[dpmac_id - 2]);
if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
env_hwconfig))
- wriop_set_phy_address(dpmac_id,
+ wriop_set_phy_address(dpmac_id, 0,
riser_phy_addr[dpmac_id - 3]);
}
dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
break;
case 4:
/* Slot housing a SGMII riser card? */
- wriop_set_phy_address(dpmac_id,
+ wriop_set_phy_address(dpmac_id, 0,
riser_phy_addr[dpmac_id - 9]);
dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
bus = mii_dev_for_muxval(EMI1_SLOT4);
if (slot == EMI_NONE)
return;
if (serdes2_prtcl == 0x47) {
- wriop_set_phy_address(dpmac_id,
+ wriop_set_phy_address(dpmac_id, 0,
riser_phy_addr[dpmac_id - 10]);
if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
env_hwconfig))
- wriop_set_phy_address(dpmac_id,
+ wriop_set_phy_address(dpmac_id, 0,
riser_phy_addr[dpmac_id - 11]);
} else {
- wriop_set_phy_address(dpmac_id,
+ wriop_set_phy_address(dpmac_id, 0,
riser_phy_addr[dpmac_id - 11]);
}
dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
break;
case 6:
/* Slot housing a SGMII riser card? */
- wriop_set_phy_address(dpmac_id,
+ wriop_set_phy_address(dpmac_id, 0,
riser_phy_addr[dpmac_id - 13]);
dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
bus = mii_dev_for_muxval(EMI1_SLOT6);
switch (++slot) {
case 1:
/* Slot housing a QSGMII riser card? */
- wriop_set_phy_address(dpmac_id, dpmac_id - 1);
+ wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
bus = mii_dev_for_muxval(EMI1_SLOT1);
wriop_set_mdio(dpmac_id, bus);
* the XAUI card is used for the XFI MAC, which will cause
* error.
*/
- wriop_set_phy_address(i, i + 4);
+ wriop_set_phy_address(i, 0, i + 4);
ls2080a_qds_enable_SFP_TX(SFP_TX);
break;
switch (srds_s1) {
case 0x2A:
- wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
- wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
- wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
- wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
- wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
- wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
+ wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
+ wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
+ wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
+ wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2);
+ wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3);
+ wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4);
break;
case 0x4B:
- wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
- wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
- wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
- wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
+ wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
+ wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
+ wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
break;
default:
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
struct phy_device *phydev = NULL;
struct mii_dev *bus;
- int ret;
+ int phy_addr, phy_num;
+ int ret = 0;
bus = wriop_get_mdio(priv->dpmac_id);
if (bus == NULL)
return 0;
- phydev = phy_connect(bus, wriop_get_phy_address(priv->dpmac_id),
- dev, wriop_get_enet_if(priv->dpmac_id));
- if (!phydev) {
- printf("Failed to connect\n");
- return -1;
- }
-
- wriop_set_phy_dev(priv->dpmac_id, phydev);
+ for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+ phy_addr = wriop_get_phy_address(priv->dpmac_id, phy_num);
+ if (phy_addr < 0)
+ continue;
- ret = phy_config(phydev);
+ phydev = phy_connect(bus, phy_addr, dev,
+ wriop_get_enet_if(priv->dpmac_id));
+ if (!phydev) {
+ printf("Failed to connect\n");
+ ret = -ENODEV;
+ break;
+ }
+ wriop_set_phy_dev(priv->dpmac_id, phy_num, phydev);
+ ret = phy_config(phydev);
+ if (ret)
+ break;
+ }
if (ret) {
- free(phydev);
- wriop_set_phy_dev(priv->dpmac_id, NULL);
+ for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+ phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
+ if (!phydev)
+ continue;
+
+ free(phydev);
+ wriop_set_phy_dev(priv->dpmac_id, phy_num, NULL);
+ }
}
return ret;
{
struct phy_device *phydev = NULL;
phy_interface_t enet_if;
+ int phy_num, phys_detected;
int err;
- /* let's start off with maximum capabilities
- */
+ /* let's start off with maximum capabilities */
enet_if = wriop_get_enet_if(priv->dpmac_id);
switch (enet_if) {
case PHY_INTERFACE_MODE_XGMII:
}
state->up = 1;
+ phys_detected = 0;
#ifdef CONFIG_PHYLIB
state->options |= DPMAC_LINK_OPT_AUTONEG;
- phydev = wriop_get_phy_dev(priv->dpmac_id);
- if (phydev) {
+ /* start the phy devices one by one and update the dpmac state */
+ for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+ phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
+ if (!phydev)
+ continue;
+
+ phys_detected++;
err = phy_startup(phydev);
if (err) {
printf("%s: Could not initialize\n", phydev->dev->name);
state->up = 0;
+ break;
}
if (phydev->link) {
state->rate = min(state->rate, (uint32_t)phydev->speed);
if (!phydev->autoneg)
state->options &= ~DPMAC_LINK_OPT_AUTONEG;
} else {
+ /* break out of loop even if one phy is down */
state->up = 0;
+ break;
}
}
#endif
- if (!phydev)
+ if (!phys_detected)
state->options &= ~DPMAC_LINK_OPT_AUTONEG;
if (!state->up) {
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
int err = 0;
struct phy_device *phydev = NULL;
+ int phy_num;
if ((net_dev->state == ETH_STATE_PASSIVE) ||
(net_dev->state == ETH_STATE_INIT))
printf("dpni_disable() failed\n");
#ifdef CONFIG_PHYLIB
- phydev = wriop_get_phy_dev(priv->dpmac_id);
- if (phydev)
- phy_shutdown(phydev);
+ for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+ phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
+ if (phydev)
+ phy_shutdown(phydev);
+ }
#endif
/* Free DPBP handle and reset. */
void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
{
phy_interface_t enet_if;
+ int phy_num;
dpmac_info[dpmac_id].enabled = 0;
dpmac_info[dpmac_id].id = 0;
- dpmac_info[dpmac_id].phy_addr = -1;
- dpmac_info[dpmac_id].phydev = NULL;
dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NONE;
enet_if = wriop_dpmac_enet_if(dpmac_id, lane_prtcl);
dpmac_info[dpmac_id].id = dpmac_id;
dpmac_info[dpmac_id].enet_if = enet_if;
}
+ for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+ dpmac_info[dpmac_id].phydev[phy_num] = NULL;
+ dpmac_info[dpmac_id].phy_addr[phy_num] = -1;
+ }
}
void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if)
{
+ int phy_num;
+
dpmac_info[dpmac_id].enabled = 1;
dpmac_info[dpmac_id].id = dpmac_id;
- dpmac_info[dpmac_id].phy_addr = -1;
dpmac_info[dpmac_id].enet_if = enet_if;
- dpmac_info[dpmac_id].phydev = NULL;
+ for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+ dpmac_info[dpmac_id].phydev[phy_num] = NULL;
+ dpmac_info[dpmac_id].phy_addr[phy_num] = -1;
+ }
}
return -1;
}
-void wriop_disable_dpmac(int dpmac_id)
+int wriop_disable_dpmac(int dpmac_id)
{
int i = wriop_dpmac_to_index(dpmac_id);
if (i == -1)
- return;
+ return -ENODEV;
dpmac_info[i].enabled = 0;
wriop_dpmac_disable(dpmac_id);
+
+ return 0;
}
-void wriop_enable_dpmac(int dpmac_id)
+int wriop_enable_dpmac(int dpmac_id)
{
int i = wriop_dpmac_to_index(dpmac_id);
if (i == -1)
- return;
+ return -ENODEV;
dpmac_info[i].enabled = 1;
wriop_dpmac_enable(dpmac_id);
+
+ return 0;
}
-u8 wriop_is_enabled_dpmac(int dpmac_id)
+int wriop_is_enabled_dpmac(int dpmac_id)
{
int i = wriop_dpmac_to_index(dpmac_id);
if (i == -1)
- return -1;
+ return -ENODEV;
return dpmac_info[i].enabled;
}
-void wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
+int wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
{
int i = wriop_dpmac_to_index(dpmac_id);
if (i == -1)
- return;
+ return -ENODEV;
dpmac_info[i].bus = bus;
+
+ return 0;
}
struct mii_dev *wriop_get_mdio(int dpmac_id)
return dpmac_info[i].bus;
}
-void wriop_set_phy_address(int dpmac_id, int address)
+int wriop_set_phy_address(int dpmac_id, int phy_num, int address)
{
int i = wriop_dpmac_to_index(dpmac_id);
if (i == -1)
- return;
+ return -ENODEV;
+ if (phy_num < 0 || phy_num >= WRIOP_MAX_PHY_NUM)
+ return -EINVAL;
+
+ dpmac_info[i].phy_addr[phy_num] = address;
- dpmac_info[i].phy_addr = address;
+ return 0;
}
-int wriop_get_phy_address(int dpmac_id)
+int wriop_get_phy_address(int dpmac_id, int phy_num)
{
int i = wriop_dpmac_to_index(dpmac_id);
if (i == -1)
- return -1;
+ return -ENODEV;
+ if (phy_num < 0 || phy_num >= WRIOP_MAX_PHY_NUM)
+ return -EINVAL;
- return dpmac_info[i].phy_addr;
+ return dpmac_info[i].phy_addr[phy_num];
}
-void wriop_set_phy_dev(int dpmac_id, struct phy_device *phydev)
+int wriop_set_phy_dev(int dpmac_id, int phy_num, struct phy_device *phydev)
{
int i = wriop_dpmac_to_index(dpmac_id);
if (i == -1)
- return;
+ return -ENODEV;
+ if (phy_num < 0 || phy_num >= WRIOP_MAX_PHY_NUM)
+ return -EINVAL;
- dpmac_info[i].phydev = phydev;
+ dpmac_info[i].phydev[phy_num] = phydev;
+
+ return 0;
}
-struct phy_device *wriop_get_phy_dev(int dpmac_id)
+struct phy_device *wriop_get_phy_dev(int dpmac_id, int phy_num)
{
int i = wriop_dpmac_to_index(dpmac_id);
if (i == -1)
return NULL;
+ if (phy_num < 0 || phy_num >= WRIOP_MAX_PHY_NUM)
+ return NULL;
- return dpmac_info[i].phydev;
+ return dpmac_info[i].phydev[phy_num];
}
phy_interface_t wriop_get_enet_if(int dpmac_id)
#ifndef __LDPAA_WRIOP_H
#define __LDPAA_WRIOP_H
- #include <phy.h>
+#include <phy.h>
+
+#define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0"
+#define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1"
+#define WRIOP_MAX_PHY_NUM 2
enum wriop_port {
WRIOP1_DPMAC1 = 1,
u8 enabled;
u8 id;
u8 board_mux;
- int phy_addr;
+ int phy_addr[WRIOP_MAX_PHY_NUM];
phy_interface_t enet_if;
- struct phy_device *phydev;
+ struct phy_device *phydev[WRIOP_MAX_PHY_NUM];
struct mii_dev *bus;
};
extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
-#define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0"
-#define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1"
-
-void wriop_init_dpmac(int, int, int);
-void wriop_disable_dpmac(int);
-void wriop_enable_dpmac(int);
-u8 wriop_is_enabled_dpmac(int dpmac_id);
-void wriop_set_mdio(int, struct mii_dev *);
-struct mii_dev *wriop_get_mdio(int);
-void wriop_set_phy_address(int, int);
-int wriop_get_phy_address(int);
-void wriop_set_phy_dev(int, struct phy_device *);
-struct phy_device *wriop_get_phy_dev(int);
-phy_interface_t wriop_get_enet_if(int);
+void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl);
+void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if);
+int wriop_disable_dpmac(int dpmac_id);
+int wriop_enable_dpmac(int dpmac_id);
+int wriop_is_enabled_dpmac(int dpmac_id);
+int wriop_set_mdio(int dpmac_id, struct mii_dev *bus);
+struct mii_dev *wriop_get_mdio(int dpmac_id);
+int wriop_set_phy_address(int dpmac_id, int phy_num, int address);
+int wriop_get_phy_address(int dpmac_id, int phy_num);
+int wriop_set_phy_dev(int dpmac_id, int phy_num, struct phy_device *phydev);
+struct phy_device *wriop_get_phy_dev(int dpmac_id, int phy_num);
+phy_interface_t wriop_get_enet_if(int dpmac_id);
-void wriop_dpmac_disable(int);
-void wriop_dpmac_enable(int);
-phy_interface_t wriop_dpmac_enet_if(int, int);
-void wriop_init_dpmac_qsgmii(int, int);
+void wriop_dpmac_disable(int dpmac_id);
+void wriop_dpmac_enable(int dpmac_id);
+phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl);
+void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl);
void wriop_init_rgmii(void);
-void wriop_init_dpmac_enet_if(int , phy_interface_t);
#endif /* __LDPAA_WRIOP_H */