st,stm32mp135f-dk)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
;;
+st,stm32mp157c-dk2 | \
+st,stm32mp157c-dk2-scmi)
+ ucidef_set_interface_lan "eth0"
+ ;;
esac
board_config_flush
SUPPORTED_DEVICES := st,stm32mp135f-dk
endef
-TARGET_DEVICES += stm32mp135f-dk
+define Device/stm32mp157c-dk2
+ DEVICE_MODEL := STM32MP157C-DK2
+ DEVICE_DTS := stm32mp157c-dk2
+ SUPPORTED_DEVICES := st,stm32mp157c-dk2 \
+ st,stm32mp157f-dk2
+endef
+
+define Device/stm32mp157c-dk2-scmi
+ DEVICE_MODEL := STM32MP157C-DK2
+ DEVICE_VARIANT := SCMI
+ DEVICE_DTS := stm32mp157c-dk2-scmi
+ SUPPORTED_DEVICES := st,stm32mp157c-dk2-scmi \
+ st,stm32mp157f-dk2-scmi
+endef
+
+TARGET_DEVICES += stm32mp135f-dk \
+ stm32mp157c-dk2 \
+ stm32mp157c-dk2-scmi
$(eval $(call BuildImage))
+++ /dev/null
-From d788961c5b25d9d822c4230bfbc536a6736b91ff Mon Sep 17 00:00:00 2001
-Date: Fri, 5 Jan 2024 14:04:03 +0100
-Subject: [PATCH 1/5] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x
- boards
-
-ETZPC is a firewall controller. Put all peripherals filtered by the
-ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for
-backward compatibility.
-
----
- arch/arm/boot/dts/st/stm32mp131.dtsi | 1020 +++++++++++++------------
- arch/arm/boot/dts/st/stm32mp133.dtsi | 50 +-
- arch/arm/boot/dts/st/stm32mp13xc.dtsi | 18 +-
- arch/arm/boot/dts/st/stm32mp13xf.dtsi | 18 +-
- 4 files changed, 569 insertions(+), 537 deletions(-)
-
---- a/arch/arm/boot/dts/st/stm32mp131.dtsi
-+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
-@@ -745,340 +745,6 @@
- dma-channels = <16>;
- };
-
-- adc_2: adc@48004000 {
-- compatible = "st,stm32mp13-adc-core";
-- reg = <0x48004000 0x400>;
-- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc ADC2>, <&rcc ADC2_K>;
-- clock-names = "bus", "adc";
-- interrupt-controller;
-- #interrupt-cells = <1>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- status = "disabled";
--
-- adc2: adc@0 {
-- compatible = "st,stm32mp13-adc";
-- #io-channel-cells = <1>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg = <0x0>;
-- interrupt-parent = <&adc_2>;
-- interrupts = <0>;
-- dmas = <&dmamux1 10 0x400 0x80000001>;
-- dma-names = "rx";
-- status = "disabled";
--
-- channel@13 {
-- reg = <13>;
-- label = "vrefint";
-- };
-- channel@14 {
-- reg = <14>;
-- label = "vddcore";
-- };
-- channel@16 {
-- reg = <16>;
-- label = "vddcpu";
-- };
-- channel@17 {
-- reg = <17>;
-- label = "vddq_ddr";
-- };
-- };
-- };
--
-- usbotg_hs: usb@49000000 {
-- compatible = "st,stm32mp15-hsotg", "snps,dwc2";
-- reg = <0x49000000 0x40000>;
-- clocks = <&rcc USBO_K>;
-- clock-names = "otg";
-- resets = <&rcc USBO_R>;
-- reset-names = "dwc2";
-- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-- g-rx-fifo-size = <512>;
-- g-np-tx-fifo-size = <32>;
-- g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
-- dr_mode = "otg";
-- otg-rev = <0x200>;
-- usb33d-supply = <&scmi_usb33>;
-- status = "disabled";
-- };
--
-- usart1: serial@4c000000 {
-- compatible = "st,stm32h7-uart";
-- reg = <0x4c000000 0x400>;
-- interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc USART1_K>;
-- resets = <&rcc USART1_R>;
-- wakeup-source;
-- dmas = <&dmamux1 41 0x400 0x5>,
-- <&dmamux1 42 0x400 0x1>;
-- dma-names = "rx", "tx";
-- status = "disabled";
-- };
--
-- usart2: serial@4c001000 {
-- compatible = "st,stm32h7-uart";
-- reg = <0x4c001000 0x400>;
-- interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc USART2_K>;
-- resets = <&rcc USART2_R>;
-- wakeup-source;
-- dmas = <&dmamux1 43 0x400 0x5>,
-- <&dmamux1 44 0x400 0x1>;
-- dma-names = "rx", "tx";
-- status = "disabled";
-- };
--
-- i2s4: audio-controller@4c002000 {
-- compatible = "st,stm32h7-i2s";
-- reg = <0x4c002000 0x400>;
-- #sound-dai-cells = <0>;
-- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-- dmas = <&dmamux1 83 0x400 0x01>,
-- <&dmamux1 84 0x400 0x01>;
-- dma-names = "rx", "tx";
-- status = "disabled";
-- };
--
-- spi4: spi@4c002000 {
-- compatible = "st,stm32h7-spi";
-- reg = <0x4c002000 0x400>;
-- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc SPI4_K>;
-- resets = <&rcc SPI4_R>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- dmas = <&dmamux1 83 0x400 0x01>,
-- <&dmamux1 84 0x400 0x01>;
-- dma-names = "rx", "tx";
-- status = "disabled";
-- };
--
-- spi5: spi@4c003000 {
-- compatible = "st,stm32h7-spi";
-- reg = <0x4c003000 0x400>;
-- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc SPI5_K>;
-- resets = <&rcc SPI5_R>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- dmas = <&dmamux1 85 0x400 0x01>,
-- <&dmamux1 86 0x400 0x01>;
-- dma-names = "rx", "tx";
-- status = "disabled";
-- };
--
-- i2c3: i2c@4c004000 {
-- compatible = "st,stm32mp13-i2c";
-- reg = <0x4c004000 0x400>;
-- interrupt-names = "event", "error";
-- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
-- <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc I2C3_K>;
-- resets = <&rcc I2C3_R>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- dmas = <&dmamux1 73 0x400 0x1>,
-- <&dmamux1 74 0x400 0x1>;
-- dma-names = "rx", "tx";
-- st,syscfg-fmp = <&syscfg 0x4 0x4>;
-- i2c-analog-filter;
-- status = "disabled";
-- };
--
-- i2c4: i2c@4c005000 {
-- compatible = "st,stm32mp13-i2c";
-- reg = <0x4c005000 0x400>;
-- interrupt-names = "event", "error";
-- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
-- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc I2C4_K>;
-- resets = <&rcc I2C4_R>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- dmas = <&dmamux1 75 0x400 0x1>,
-- <&dmamux1 76 0x400 0x1>;
-- dma-names = "rx", "tx";
-- st,syscfg-fmp = <&syscfg 0x4 0x8>;
-- i2c-analog-filter;
-- status = "disabled";
-- };
--
-- i2c5: i2c@4c006000 {
-- compatible = "st,stm32mp13-i2c";
-- reg = <0x4c006000 0x400>;
-- interrupt-names = "event", "error";
-- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc I2C5_K>;
-- resets = <&rcc I2C5_R>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- dmas = <&dmamux1 115 0x400 0x1>,
-- <&dmamux1 116 0x400 0x1>;
-- dma-names = "rx", "tx";
-- st,syscfg-fmp = <&syscfg 0x4 0x10>;
-- i2c-analog-filter;
-- status = "disabled";
-- };
--
-- timers12: timer@4c007000 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- compatible = "st,stm32-timers";
-- reg = <0x4c007000 0x400>;
-- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
-- interrupt-names = "global";
-- clocks = <&rcc TIM12_K>;
-- clock-names = "int";
-- status = "disabled";
--
-- pwm {
-- compatible = "st,stm32-pwm";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- timer@11 {
-- compatible = "st,stm32h7-timer-trigger";
-- reg = <11>;
-- status = "disabled";
-- };
-- };
--
-- timers13: timer@4c008000 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- compatible = "st,stm32-timers";
-- reg = <0x4c008000 0x400>;
-- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-- interrupt-names = "global";
-- clocks = <&rcc TIM13_K>;
-- clock-names = "int";
-- status = "disabled";
--
-- pwm {
-- compatible = "st,stm32-pwm";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- timer@12 {
-- compatible = "st,stm32h7-timer-trigger";
-- reg = <12>;
-- status = "disabled";
-- };
-- };
--
-- timers14: timer@4c009000 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- compatible = "st,stm32-timers";
-- reg = <0x4c009000 0x400>;
-- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-- interrupt-names = "global";
-- clocks = <&rcc TIM14_K>;
-- clock-names = "int";
-- status = "disabled";
--
-- pwm {
-- compatible = "st,stm32-pwm";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- timer@13 {
-- compatible = "st,stm32h7-timer-trigger";
-- reg = <13>;
-- status = "disabled";
-- };
-- };
--
-- timers15: timer@4c00a000 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- compatible = "st,stm32-timers";
-- reg = <0x4c00a000 0x400>;
-- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-- interrupt-names = "global";
-- clocks = <&rcc TIM15_K>;
-- clock-names = "int";
-- dmas = <&dmamux1 105 0x400 0x1>,
-- <&dmamux1 106 0x400 0x1>,
-- <&dmamux1 107 0x400 0x1>,
-- <&dmamux1 108 0x400 0x1>;
-- dma-names = "ch1", "up", "trig", "com";
-- status = "disabled";
--
-- pwm {
-- compatible = "st,stm32-pwm";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- timer@14 {
-- compatible = "st,stm32h7-timer-trigger";
-- reg = <14>;
-- status = "disabled";
-- };
-- };
--
-- timers16: timer@4c00b000 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- compatible = "st,stm32-timers";
-- reg = <0x4c00b000 0x400>;
-- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
-- interrupt-names = "global";
-- clocks = <&rcc TIM16_K>;
-- clock-names = "int";
-- dmas = <&dmamux1 109 0x400 0x1>,
-- <&dmamux1 110 0x400 0x1>;
-- dma-names = "ch1", "up";
-- status = "disabled";
--
-- pwm {
-- compatible = "st,stm32-pwm";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- timer@15 {
-- compatible = "st,stm32h7-timer-trigger";
-- reg = <15>;
-- status = "disabled";
-- };
-- };
--
-- timers17: timer@4c00c000 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- compatible = "st,stm32-timers";
-- reg = <0x4c00c000 0x400>;
-- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-- interrupt-names = "global";
-- clocks = <&rcc TIM17_K>;
-- clock-names = "int";
-- dmas = <&dmamux1 111 0x400 0x1>,
-- <&dmamux1 112 0x400 0x1>;
-- dma-names = "ch1", "up";
-- status = "disabled";
--
-- pwm {
-- compatible = "st,stm32-pwm";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- timer@16 {
-- compatible = "st,stm32h7-timer-trigger";
-- reg = <16>;
-- status = "disabled";
-- };
-- };
--
- rcc: rcc@50000000 {
- compatible = "st,stm32mp13-rcc", "syscon";
- reg = <0x50000000 0x1000>;
-@@ -1105,69 +771,6 @@
- clocks = <&rcc SYSCFG>;
- };
-
-- lptimer2: timer@50021000 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- compatible = "st,stm32-lptimer";
-- reg = <0x50021000 0x400>;
-- interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc LPTIM2_K>;
-- clock-names = "mux";
-- wakeup-source;
-- status = "disabled";
--
-- pwm {
-- compatible = "st,stm32-pwm-lp";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- trigger@1 {
-- compatible = "st,stm32-lptimer-trigger";
-- reg = <1>;
-- status = "disabled";
-- };
--
-- counter {
-- compatible = "st,stm32-lptimer-counter";
-- status = "disabled";
-- };
--
-- timer {
-- compatible = "st,stm32-lptimer-timer";
-- status = "disabled";
-- };
-- };
--
-- lptimer3: timer@50022000 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- compatible = "st,stm32-lptimer";
-- reg = <0x50022000 0x400>;
-- interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc LPTIM3_K>;
-- clock-names = "mux";
-- wakeup-source;
-- status = "disabled";
--
-- pwm {
-- compatible = "st,stm32-pwm-lp";
-- #pwm-cells = <3>;
-- status = "disabled";
-- };
--
-- trigger@2 {
-- compatible = "st,stm32-lptimer-trigger";
-- reg = <2>;
-- status = "disabled";
-- };
--
-- timer {
-- compatible = "st,stm32-lptimer-timer";
-- status = "disabled";
-- };
-- };
--
- lptimer4: timer@50023000 {
- compatible = "st,stm32-lptimer";
- reg = <0x50023000 0x400>;
-@@ -1220,79 +823,10 @@
- dma-requests = <48>;
- };
-
-- fmc: memory-controller@58002000 {
-- compatible = "st,stm32mp1-fmc2-ebi";
-- reg = <0x58002000 0x1000>;
-- ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
-- <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
-- <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
-- <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
-- <4 0 0x80000000 0x10000000>; /* NAND */
-- #address-cells = <2>;
-- #size-cells = <1>;
-- clocks = <&rcc FMC_K>;
-- resets = <&rcc FMC_R>;
-- status = "disabled";
--
-- nand-controller@4,0 {
-- compatible = "st,stm32mp1-fmc2-nfc";
-- reg = <4 0x00000000 0x1000>,
-- <4 0x08010000 0x1000>,
-- <4 0x08020000 0x1000>,
-- <4 0x01000000 0x1000>,
-- <4 0x09010000 0x1000>,
-- <4 0x09020000 0x1000>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-- dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
-- <&mdma 24 0x2 0x12000a08 0x0 0x0>,
-- <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
-- dma-names = "tx", "rx", "ecc";
-- status = "disabled";
-- };
-- };
--
-- qspi: spi@58003000 {
-- compatible = "st,stm32f469-qspi";
-- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
-- reg-names = "qspi", "qspi_mm";
-- #address-cells = <1>;
-- #size-cells = <0>;
-- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-- dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
-- <&mdma 26 0x2 0x10100008 0x0 0x0>;
-- dma-names = "tx", "rx";
-- clocks = <&rcc QSPI_K>;
-- resets = <&rcc QSPI_R>;
-- status = "disabled";
-- };
--
-- sdmmc1: mmc@58005000 {
-- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-- arm,primecell-periphid = <0x20253180>;
-- reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
-- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc SDMMC1_K>;
-- clock-names = "apb_pclk";
-- resets = <&rcc SDMMC1_R>;
-- cap-sd-highspeed;
-- cap-mmc-highspeed;
-- max-frequency = <130000000>;
-- status = "disabled";
-- };
--
-- sdmmc2: mmc@58007000 {
-- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-- arm,primecell-periphid = <0x20253180>;
-- reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
-- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc SDMMC2_K>;
-- clock-names = "apb_pclk";
-- resets = <&rcc SDMMC2_R>;
-- cap-sd-highspeed;
-- cap-mmc-highspeed;
-- max-frequency = <130000000>;
-+ crc1: crc@58009000 {
-+ compatible = "st,stm32f7-crc";
-+ reg = <0x58009000 0x400>;
-+ clocks = <&rcc CRC1>;
- status = "disabled";
- };
-
-@@ -1323,29 +857,6 @@
- status = "disabled";
- };
-
-- usbphyc: usbphyc@5a006000 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- #clock-cells = <0>;
-- compatible = "st,stm32mp1-usbphyc";
-- reg = <0x5a006000 0x1000>;
-- clocks = <&rcc USBPHY_K>;
-- resets = <&rcc USBPHY_R>;
-- vdda1v1-supply = <&scmi_reg11>;
-- vdda1v8-supply = <&scmi_reg18>;
-- status = "disabled";
--
-- usbphyc_port0: usb-phy@0 {
-- #phy-cells = <0>;
-- reg = <0>;
-- };
--
-- usbphyc_port1: usb-phy@1 {
-- #phy-cells = <1>;
-- reg = <1>;
-- };
-- };
--
- rtc: rtc@5c004000 {
- compatible = "st,stm32mp1-rtc";
- reg = <0x5c004000 0x400>;
-@@ -1374,6 +885,529 @@
- };
- };
-
-+ etzpc: bus@5c007000 {
-+ compatible = "simple-bus";
-+ reg = <0x5c007000 0x400>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges;
-+
-+ adc_2: adc@48004000 {
-+ compatible = "st,stm32mp13-adc-core";
-+ reg = <0x48004000 0x400>;
-+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc ADC2>, <&rcc ADC2_K>;
-+ clock-names = "bus", "adc";
-+ interrupt-controller;
-+ #interrupt-cells = <1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+
-+ adc2: adc@0 {
-+ compatible = "st,stm32mp13-adc";
-+ #io-channel-cells = <1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x0>;
-+ interrupt-parent = <&adc_2>;
-+ interrupts = <0>;
-+ dmas = <&dmamux1 10 0x400 0x80000001>;
-+ dma-names = "rx";
-+ status = "disabled";
-+
-+ channel@13 {
-+ reg = <13>;
-+ label = "vrefint";
-+ };
-+ channel@14 {
-+ reg = <14>;
-+ label = "vddcore";
-+ };
-+ channel@16 {
-+ reg = <16>;
-+ label = "vddcpu";
-+ };
-+ channel@17 {
-+ reg = <17>;
-+ label = "vddq_ddr";
-+ };
-+ };
-+ };
-+
-+ usbotg_hs: usb@49000000 {
-+ compatible = "st,stm32mp15-hsotg", "snps,dwc2";
-+ reg = <0x49000000 0x40000>;
-+ clocks = <&rcc USBO_K>;
-+ clock-names = "otg";
-+ resets = <&rcc USBO_R>;
-+ reset-names = "dwc2";
-+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-+ g-rx-fifo-size = <512>;
-+ g-np-tx-fifo-size = <32>;
-+ g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
-+ dr_mode = "otg";
-+ otg-rev = <0x200>;
-+ usb33d-supply = <&scmi_usb33>;
-+ status = "disabled";
-+ };
-+
-+ usart1: serial@4c000000 {
-+ compatible = "st,stm32h7-uart";
-+ reg = <0x4c000000 0x400>;
-+ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc USART1_K>;
-+ resets = <&rcc USART1_R>;
-+ wakeup-source;
-+ dmas = <&dmamux1 41 0x400 0x5>,
-+ <&dmamux1 42 0x400 0x1>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
-+ usart2: serial@4c001000 {
-+ compatible = "st,stm32h7-uart";
-+ reg = <0x4c001000 0x400>;
-+ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc USART2_K>;
-+ resets = <&rcc USART2_R>;
-+ wakeup-source;
-+ dmas = <&dmamux1 43 0x400 0x5>,
-+ <&dmamux1 44 0x400 0x1>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
-+ i2s4: audio-controller@4c002000 {
-+ compatible = "st,stm32h7-i2s";
-+ reg = <0x4c002000 0x400>;
-+ #sound-dai-cells = <0>;
-+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-+ dmas = <&dmamux1 83 0x400 0x01>,
-+ <&dmamux1 84 0x400 0x01>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
-+ spi4: spi@4c002000 {
-+ compatible = "st,stm32h7-spi";
-+ reg = <0x4c002000 0x400>;
-+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc SPI4_K>;
-+ resets = <&rcc SPI4_R>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ dmas = <&dmamux1 83 0x400 0x01>,
-+ <&dmamux1 84 0x400 0x01>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
-+ spi5: spi@4c003000 {
-+ compatible = "st,stm32h7-spi";
-+ reg = <0x4c003000 0x400>;
-+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc SPI5_K>;
-+ resets = <&rcc SPI5_R>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ dmas = <&dmamux1 85 0x400 0x01>,
-+ <&dmamux1 86 0x400 0x01>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
-+ i2c3: i2c@4c004000 {
-+ compatible = "st,stm32mp13-i2c";
-+ reg = <0x4c004000 0x400>;
-+ interrupt-names = "event", "error";
-+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc I2C3_K>;
-+ resets = <&rcc I2C3_R>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ dmas = <&dmamux1 73 0x400 0x1>,
-+ <&dmamux1 74 0x400 0x1>;
-+ dma-names = "rx", "tx";
-+ st,syscfg-fmp = <&syscfg 0x4 0x4>;
-+ i2c-analog-filter;
-+ status = "disabled";
-+ };
-+
-+ i2c4: i2c@4c005000 {
-+ compatible = "st,stm32mp13-i2c";
-+ reg = <0x4c005000 0x400>;
-+ interrupt-names = "event", "error";
-+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc I2C4_K>;
-+ resets = <&rcc I2C4_R>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ dmas = <&dmamux1 75 0x400 0x1>,
-+ <&dmamux1 76 0x400 0x1>;
-+ dma-names = "rx", "tx";
-+ st,syscfg-fmp = <&syscfg 0x4 0x8>;
-+ i2c-analog-filter;
-+ status = "disabled";
-+ };
-+
-+ i2c5: i2c@4c006000 {
-+ compatible = "st,stm32mp13-i2c";
-+ reg = <0x4c006000 0x400>;
-+ interrupt-names = "event", "error";
-+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc I2C5_K>;
-+ resets = <&rcc I2C5_R>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ dmas = <&dmamux1 115 0x400 0x1>,
-+ <&dmamux1 116 0x400 0x1>;
-+ dma-names = "rx", "tx";
-+ st,syscfg-fmp = <&syscfg 0x4 0x10>;
-+ i2c-analog-filter;
-+ status = "disabled";
-+ };
-+
-+ timers12: timer@4c007000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "st,stm32-timers";
-+ reg = <0x4c007000 0x400>;
-+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "global";
-+ clocks = <&rcc TIM12_K>;
-+ clock-names = "int";
-+ status = "disabled";
-+
-+ pwm {
-+ compatible = "st,stm32-pwm";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ timer@11 {
-+ compatible = "st,stm32h7-timer-trigger";
-+ reg = <11>;
-+ status = "disabled";
-+ };
-+ };
-+
-+ timers13: timer@4c008000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "st,stm32-timers";
-+ reg = <0x4c008000 0x400>;
-+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "global";
-+ clocks = <&rcc TIM13_K>;
-+ clock-names = "int";
-+ status = "disabled";
-+
-+ pwm {
-+ compatible = "st,stm32-pwm";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ timer@12 {
-+ compatible = "st,stm32h7-timer-trigger";
-+ reg = <12>;
-+ status = "disabled";
-+ };
-+ };
-+
-+ timers14: timer@4c009000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "st,stm32-timers";
-+ reg = <0x4c009000 0x400>;
-+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "global";
-+ clocks = <&rcc TIM14_K>;
-+ clock-names = "int";
-+ status = "disabled";
-+
-+ pwm {
-+ compatible = "st,stm32-pwm";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ timer@13 {
-+ compatible = "st,stm32h7-timer-trigger";
-+ reg = <13>;
-+ status = "disabled";
-+ };
-+ };
-+
-+ timers15: timer@4c00a000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "st,stm32-timers";
-+ reg = <0x4c00a000 0x400>;
-+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "global";
-+ clocks = <&rcc TIM15_K>;
-+ clock-names = "int";
-+ dmas = <&dmamux1 105 0x400 0x1>,
-+ <&dmamux1 106 0x400 0x1>,
-+ <&dmamux1 107 0x400 0x1>,
-+ <&dmamux1 108 0x400 0x1>;
-+ dma-names = "ch1", "up", "trig", "com";
-+ status = "disabled";
-+
-+ pwm {
-+ compatible = "st,stm32-pwm";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ timer@14 {
-+ compatible = "st,stm32h7-timer-trigger";
-+ reg = <14>;
-+ status = "disabled";
-+ };
-+ };
-+
-+ timers16: timer@4c00b000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "st,stm32-timers";
-+ reg = <0x4c00b000 0x400>;
-+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "global";
-+ clocks = <&rcc TIM16_K>;
-+ clock-names = "int";
-+ dmas = <&dmamux1 109 0x400 0x1>,
-+ <&dmamux1 110 0x400 0x1>;
-+ dma-names = "ch1", "up";
-+ status = "disabled";
-+
-+ pwm {
-+ compatible = "st,stm32-pwm";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ timer@15 {
-+ compatible = "st,stm32h7-timer-trigger";
-+ reg = <15>;
-+ status = "disabled";
-+ };
-+ };
-+
-+ timers17: timer@4c00c000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "st,stm32-timers";
-+ reg = <0x4c00c000 0x400>;
-+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "global";
-+ clocks = <&rcc TIM17_K>;
-+ clock-names = "int";
-+ dmas = <&dmamux1 111 0x400 0x1>,
-+ <&dmamux1 112 0x400 0x1>;
-+ dma-names = "ch1", "up";
-+ status = "disabled";
-+
-+ pwm {
-+ compatible = "st,stm32-pwm";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ timer@16 {
-+ compatible = "st,stm32h7-timer-trigger";
-+ reg = <16>;
-+ status = "disabled";
-+ };
-+ };
-+
-+ lptimer2: timer@50021000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "st,stm32-lptimer";
-+ reg = <0x50021000 0x400>;
-+ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc LPTIM2_K>;
-+ clock-names = "mux";
-+ wakeup-source;
-+ status = "disabled";
-+
-+ pwm {
-+ compatible = "st,stm32-pwm-lp";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ trigger@1 {
-+ compatible = "st,stm32-lptimer-trigger";
-+ reg = <1>;
-+ status = "disabled";
-+ };
-+
-+ counter {
-+ compatible = "st,stm32-lptimer-counter";
-+ status = "disabled";
-+ };
-+
-+ timer {
-+ compatible = "st,stm32-lptimer-timer";
-+ status = "disabled";
-+ };
-+ };
-+
-+ lptimer3: timer@50022000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "st,stm32-lptimer";
-+ reg = <0x50022000 0x400>;
-+ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc LPTIM3_K>;
-+ clock-names = "mux";
-+ wakeup-source;
-+ status = "disabled";
-+
-+ pwm {
-+ compatible = "st,stm32-pwm-lp";
-+ #pwm-cells = <3>;
-+ status = "disabled";
-+ };
-+
-+ trigger@2 {
-+ compatible = "st,stm32-lptimer-trigger";
-+ reg = <2>;
-+ status = "disabled";
-+ };
-+
-+ timer {
-+ compatible = "st,stm32-lptimer-timer";
-+ status = "disabled";
-+ };
-+ };
-+
-+ hash: hash@54003000 {
-+ compatible = "st,stm32mp13-hash";
-+ reg = <0x54003000 0x400>;
-+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc HASH1>;
-+ resets = <&rcc HASH1_R>;
-+ dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>;
-+ dma-names = "in";
-+ status = "disabled";
-+ };
-+
-+ rng: rng@54004000 {
-+ compatible = "st,stm32mp13-rng";
-+ reg = <0x54004000 0x400>;
-+ clocks = <&rcc RNG1_K>;
-+ resets = <&rcc RNG1_R>;
-+ status = "disabled";
-+ };
-+
-+ fmc: memory-controller@58002000 {
-+ compatible = "st,stm32mp1-fmc2-ebi";
-+ reg = <0x58002000 0x1000>;
-+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
-+ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
-+ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
-+ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
-+ <4 0 0x80000000 0x10000000>; /* NAND */
-+ #address-cells = <2>;
-+ #size-cells = <1>;
-+ clocks = <&rcc FMC_K>;
-+ resets = <&rcc FMC_R>;
-+ status = "disabled";
-+
-+ nand-controller@4,0 {
-+ compatible = "st,stm32mp1-fmc2-nfc";
-+ reg = <4 0x00000000 0x1000>,
-+ <4 0x08010000 0x1000>,
-+ <4 0x08020000 0x1000>,
-+ <4 0x01000000 0x1000>,
-+ <4 0x09010000 0x1000>,
-+ <4 0x09020000 0x1000>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-+ dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
-+ <&mdma 24 0x2 0x12000a08 0x0 0x0>,
-+ <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
-+ dma-names = "tx", "rx", "ecc";
-+ status = "disabled";
-+ };
-+ };
-+
-+ qspi: spi@58003000 {
-+ compatible = "st,stm32f469-qspi";
-+ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
-+ reg-names = "qspi", "qspi_mm";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-+ dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
-+ <&mdma 26 0x2 0x10100008 0x0 0x0>;
-+ dma-names = "tx", "rx";
-+ clocks = <&rcc QSPI_K>;
-+ resets = <&rcc QSPI_R>;
-+ status = "disabled";
-+ };
-+
-+ sdmmc1: mmc@58005000 {
-+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-+ arm,primecell-periphid = <0x20253180>;
-+ reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
-+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc SDMMC1_K>;
-+ clock-names = "apb_pclk";
-+ resets = <&rcc SDMMC1_R>;
-+ cap-sd-highspeed;
-+ cap-mmc-highspeed;
-+ max-frequency = <130000000>;
-+ status = "disabled";
-+ };
-+
-+ sdmmc2: mmc@58007000 {
-+ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-+ arm,primecell-periphid = <0x20253180>;
-+ reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
-+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc SDMMC2_K>;
-+ clock-names = "apb_pclk";
-+ resets = <&rcc SDMMC2_R>;
-+ cap-sd-highspeed;
-+ cap-mmc-highspeed;
-+ max-frequency = <130000000>;
-+ status = "disabled";
-+ };
-+
-+ usbphyc: usbphyc@5a006000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ #clock-cells = <0>;
-+ compatible = "st,stm32mp1-usbphyc";
-+ reg = <0x5a006000 0x1000>;
-+ clocks = <&rcc USBPHY_K>;
-+ resets = <&rcc USBPHY_R>;
-+ vdda1v1-supply = <&scmi_reg11>;
-+ vdda1v8-supply = <&scmi_reg18>;
-+ status = "disabled";
-+
-+ usbphyc_port0: usb-phy@0 {
-+ #phy-cells = <0>;
-+ reg = <0>;
-+ };
-+
-+ usbphyc_port1: usb-phy@1 {
-+ #phy-cells = <1>;
-+ reg = <1>;
-+ };
-+ };
-+ };
-+
- /*
- * Break node order to solve dependency probe issue between
- * pinctrl and exti.
---- a/arch/arm/boot/dts/st/stm32mp133.dtsi
-+++ b/arch/arm/boot/dts/st/stm32mp133.dtsi
-@@ -33,35 +33,37 @@
- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
- status = "disabled";
- };
-+ };
-+};
-+
-+&etzpc {
-+ adc_1: adc@48003000 {
-+ compatible = "st,stm32mp13-adc-core";
-+ reg = <0x48003000 0x400>;
-+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc ADC1>, <&rcc ADC1_K>;
-+ clock-names = "bus", "adc";
-+ interrupt-controller;
-+ #interrupt-cells = <1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-
-- adc_1: adc@48003000 {
-- compatible = "st,stm32mp13-adc-core";
-- reg = <0x48003000 0x400>;
-- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc ADC1>, <&rcc ADC1_K>;
-- clock-names = "bus", "adc";
-- interrupt-controller;
-- #interrupt-cells = <1>;
-+ adc1: adc@0 {
-+ compatible = "st,stm32mp13-adc";
-+ #io-channel-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-+ reg = <0x0>;
-+ interrupt-parent = <&adc_1>;
-+ interrupts = <0>;
-+ dmas = <&dmamux1 9 0x400 0x80000001>;
-+ dma-names = "rx";
- status = "disabled";
-
-- adc1: adc@0 {
-- compatible = "st,stm32mp13-adc";
-- #io-channel-cells = <1>;
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg = <0x0>;
-- interrupt-parent = <&adc_1>;
-- interrupts = <0>;
-- dmas = <&dmamux1 9 0x400 0x80000001>;
-- dma-names = "rx";
-- status = "disabled";
--
-- channel@18 {
-- reg = <18>;
-- label = "vrefint";
-- };
-+ channel@18 {
-+ reg = <18>;
-+ label = "vrefint";
- };
- };
- };
---- a/arch/arm/boot/dts/st/stm32mp13xc.dtsi
-+++ b/arch/arm/boot/dts/st/stm32mp13xc.dtsi
-@@ -4,15 +4,13 @@
- */
-
--/ {
-- soc {
-- cryp: crypto@54002000 {
-- compatible = "st,stm32mp1-cryp";
-- reg = <0x54002000 0x400>;
-- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc CRYP1>;
-- resets = <&rcc CRYP1_R>;
-- status = "disabled";
-- };
-+&etzpc {
-+ cryp: crypto@54002000 {
-+ compatible = "st,stm32mp1-cryp";
-+ reg = <0x54002000 0x400>;
-+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc CRYP1>;
-+ resets = <&rcc CRYP1_R>;
-+ status = "disabled";
- };
- };
---- a/arch/arm/boot/dts/st/stm32mp13xf.dtsi
-+++ b/arch/arm/boot/dts/st/stm32mp13xf.dtsi
-@@ -4,15 +4,13 @@
- */
-
--/ {
-- soc {
-- cryp: crypto@54002000 {
-- compatible = "st,stm32mp1-cryp";
-- reg = <0x54002000 0x400>;
-- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&rcc CRYP1>;
-- resets = <&rcc CRYP1_R>;
-- status = "disabled";
-- };
-+&etzpc {
-+ cryp: crypto@54002000 {
-+ compatible = "st,stm32mp1-cryp";
-+ reg = <0x54002000 0x400>;
-+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&rcc CRYP1>;
-+ resets = <&rcc CRYP1_R>;
-+ status = "disabled";
- };
- };
--- /dev/null
+From 3cd1d4651cebe9776a0142ade36ff9f2e3545436 Mon Sep 17 00:00:00 2001
+Date: Mon, 1 Jul 2024 08:48:37 +0200
+Subject: [PATCH] net: stmmac: dwmac-stm32: Add test to verify if ETHCK is used
+ before checking clk rate
+
+When we want to use clock from RCC to clock Ethernet PHY (with ETHCK)
+we need to check if value of clock rate is authorized.
+If ETHCK is unused, the ETHCK frequency is 0Hz and validation fails.
+It makes no sense to validate unused ETHCK, so skip the validation.
+
+Fixes: 582ac134963e ("net: stmmac: dwmac-stm32: Separate out external clock rate validation")
+---
+ drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+@@ -195,6 +195,9 @@ static int stm32mp1_validate_ethck_rate(
+ struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
+ const u32 clk_rate = clk_get_rate(dwmac->clk_eth_ck);
+
++ if (!dwmac->enable_eth_ck)
++ return 0;
++
+ switch (plat_dat->mac_interface) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_GMII:
+++ /dev/null
-From 21ca3d7c59595d76237faebeff4f6a979cf7ae82 Mon Sep 17 00:00:00 2001
-Date: Fri, 5 Apr 2024 13:45:24 +0200
-Subject: [PATCH 2/5] ARM: dts: stm32: put ETZPC as an access controller for
- STM32MP13x boards
-
-Reference ETZPC as an access-control-provider.
-
-For more information on which peripheral is securable or supports MCU
-isolation, please read the STM32MP13 reference manual
-
----
- arch/arm/boot/dts/st/stm32mp131.dtsi | 28 ++++++++++++++++++++++++++-
- arch/arm/boot/dts/st/stm32mp133.dtsi | 1 +
- arch/arm/boot/dts/st/stm32mp13xc.dtsi | 1 +
- arch/arm/boot/dts/st/stm32mp13xf.dtsi | 1 +
- 4 files changed, 30 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/st/stm32mp131.dtsi
-+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
-@@ -886,10 +886,11 @@
- };
-
- etzpc: bus@5c007000 {
-- compatible = "simple-bus";
-+ compatible = "st,stm32-etzpc", "simple-bus";
- reg = <0x5c007000 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
-+ #access-controller-cells = <1>;
- ranges;
-
- adc_2: adc@48004000 {
-@@ -902,6 +903,7 @@
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-+ access-controllers = <&etzpc 33>;
- status = "disabled";
-
- adc2: adc@0 {
-@@ -949,6 +951,7 @@
- dr_mode = "otg";
- otg-rev = <0x200>;
- usb33d-supply = <&scmi_usb33>;
-+ access-controllers = <&etzpc 34>;
- status = "disabled";
- };
-
-@@ -962,6 +965,7 @@
- dmas = <&dmamux1 41 0x400 0x5>,
- <&dmamux1 42 0x400 0x1>;
- dma-names = "rx", "tx";
-+ access-controllers = <&etzpc 16>;
- status = "disabled";
- };
-
-@@ -975,6 +979,7 @@
- dmas = <&dmamux1 43 0x400 0x5>,
- <&dmamux1 44 0x400 0x1>;
- dma-names = "rx", "tx";
-+ access-controllers = <&etzpc 17>;
- status = "disabled";
- };
-
-@@ -986,6 +991,7 @@
- dmas = <&dmamux1 83 0x400 0x01>,
- <&dmamux1 84 0x400 0x01>;
- dma-names = "rx", "tx";
-+ access-controllers = <&etzpc 13>;
- status = "disabled";
- };
-
-@@ -1000,6 +1006,7 @@
- dmas = <&dmamux1 83 0x400 0x01>,
- <&dmamux1 84 0x400 0x01>;
- dma-names = "rx", "tx";
-+ access-controllers = <&etzpc 18>;
- status = "disabled";
- };
-
-@@ -1014,6 +1021,7 @@
- dmas = <&dmamux1 85 0x400 0x01>,
- <&dmamux1 86 0x400 0x01>;
- dma-names = "rx", "tx";
-+ access-controllers = <&etzpc 19>;
- status = "disabled";
- };
-
-@@ -1032,6 +1040,7 @@
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x4>;
- i2c-analog-filter;
-+ access-controllers = <&etzpc 20>;
- status = "disabled";
- };
-
-@@ -1050,6 +1059,7 @@
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x8>;
- i2c-analog-filter;
-+ access-controllers = <&etzpc 21>;
- status = "disabled";
- };
-
-@@ -1068,6 +1078,7 @@
- dma-names = "rx", "tx";
- st,syscfg-fmp = <&syscfg 0x4 0x10>;
- i2c-analog-filter;
-+ access-controllers = <&etzpc 22>;
- status = "disabled";
- };
-
-@@ -1080,6 +1091,7 @@
- interrupt-names = "global";
- clocks = <&rcc TIM12_K>;
- clock-names = "int";
-+ access-controllers = <&etzpc 23>;
- status = "disabled";
-
- pwm {
-@@ -1104,6 +1116,7 @@
- interrupt-names = "global";
- clocks = <&rcc TIM13_K>;
- clock-names = "int";
-+ access-controllers = <&etzpc 24>;
- status = "disabled";
-
- pwm {
-@@ -1128,6 +1141,7 @@
- interrupt-names = "global";
- clocks = <&rcc TIM14_K>;
- clock-names = "int";
-+ access-controllers = <&etzpc 25>;
- status = "disabled";
-
- pwm {
-@@ -1157,6 +1171,7 @@
- <&dmamux1 107 0x400 0x1>,
- <&dmamux1 108 0x400 0x1>;
- dma-names = "ch1", "up", "trig", "com";
-+ access-controllers = <&etzpc 26>;
- status = "disabled";
-
- pwm {
-@@ -1184,6 +1199,7 @@
- dmas = <&dmamux1 109 0x400 0x1>,
- <&dmamux1 110 0x400 0x1>;
- dma-names = "ch1", "up";
-+ access-controllers = <&etzpc 27>;
- status = "disabled";
-
- pwm {
-@@ -1211,6 +1227,7 @@
- dmas = <&dmamux1 111 0x400 0x1>,
- <&dmamux1 112 0x400 0x1>;
- dma-names = "ch1", "up";
-+ access-controllers = <&etzpc 28>;
- status = "disabled";
-
- pwm {
-@@ -1235,6 +1252,7 @@
- clocks = <&rcc LPTIM2_K>;
- clock-names = "mux";
- wakeup-source;
-+ access-controllers = <&etzpc 1>;
- status = "disabled";
-
- pwm {
-@@ -1269,6 +1287,7 @@
- clocks = <&rcc LPTIM3_K>;
- clock-names = "mux";
- wakeup-source;
-+ access-controllers = <&etzpc 2>;
- status = "disabled";
-
- pwm {
-@@ -1297,6 +1316,7 @@
- resets = <&rcc HASH1_R>;
- dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>;
- dma-names = "in";
-+ access-controllers = <&etzpc 41>;
- status = "disabled";
- };
-
-@@ -1305,6 +1325,7 @@
- reg = <0x54004000 0x400>;
- clocks = <&rcc RNG1_K>;
- resets = <&rcc RNG1_R>;
-+ access-controllers = <&etzpc 40>;
- status = "disabled";
- };
-
-@@ -1320,6 +1341,7 @@
- #size-cells = <1>;
- clocks = <&rcc FMC_K>;
- resets = <&rcc FMC_R>;
-+ access-controllers = <&etzpc 54>;
- status = "disabled";
-
- nand-controller@4,0 {
-@@ -1353,6 +1375,7 @@
- dma-names = "tx", "rx";
- clocks = <&rcc QSPI_K>;
- resets = <&rcc QSPI_R>;
-+ access-controllers = <&etzpc 55>;
- status = "disabled";
- };
-
-@@ -1367,6 +1390,7 @@
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <130000000>;
-+ access-controllers = <&etzpc 50>;
- status = "disabled";
- };
-
-@@ -1381,6 +1405,7 @@
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <130000000>;
-+ access-controllers = <&etzpc 51>;
- status = "disabled";
- };
-
-@@ -1394,6 +1419,7 @@
- resets = <&rcc USBPHY_R>;
- vdda1v1-supply = <&scmi_reg11>;
- vdda1v8-supply = <&scmi_reg18>;
-+ access-controllers = <&etzpc 5>;
- status = "disabled";
-
- usbphyc_port0: usb-phy@0 {
---- a/arch/arm/boot/dts/st/stm32mp133.dtsi
-+++ b/arch/arm/boot/dts/st/stm32mp133.dtsi
-@@ -47,6 +47,7 @@
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-+ access-controllers = <&etzpc 32>;
- status = "disabled";
-
- adc1: adc@0 {
---- a/arch/arm/boot/dts/st/stm32mp13xc.dtsi
-+++ b/arch/arm/boot/dts/st/stm32mp13xc.dtsi
-@@ -11,6 +11,7 @@
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CRYP1>;
- resets = <&rcc CRYP1_R>;
-+ access-controllers = <&etzpc 42>;
- status = "disabled";
- };
- };
---- a/arch/arm/boot/dts/st/stm32mp13xf.dtsi
-+++ b/arch/arm/boot/dts/st/stm32mp13xf.dtsi
-@@ -11,6 +11,7 @@
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&rcc CRYP1>;
- resets = <&rcc CRYP1_R>;
-+ access-controllers = <&etzpc 42>;
- status = "disabled";
- };
- };
--- /dev/null
+From f8dbe58e2f1a3c091531b3f8ef86b393ceee67d1 Mon Sep 17 00:00:00 2001
+Date: Mon, 1 Jul 2024 08:48:38 +0200
+Subject: [PATCH] net: stmmac: dwmac-stm32: update err status in case different
+ of stm32mp13
+
+The mask parameter of syscfg property is mandatory for MP13 but
+optional for all other cases.
+The function should not return error code because for non-MP13
+the missing syscfg phandle in DT is not considered an error.
+So reset err to 0 in that case to support existing DTs without
+syscfg phandle.
+
+Fixes: 50bbc0393114 ("net: stmmac: dwmac-stm32: add management of stm32mp13 for stm32")
+---
+ drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+@@ -371,10 +371,12 @@ static int stm32_dwmac_parse_data(struct
+ dwmac->mode_mask = SYSCFG_MP1_ETH_MASK;
+ err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask);
+ if (err) {
+- if (dwmac->ops->is_mp13)
++ if (dwmac->ops->is_mp13) {
+ dev_err(dev, "Sysconfig register mask must be set (%d)\n", err);
+- else
++ } else {
+ dev_dbg(dev, "Warning sysconfig register mask not set\n");
++ err = 0;
++ }
+ }
+
+ return err;
+++ /dev/null
-From b1468a44e0c0f43a06e027efeff4183b3aee0cf7 Mon Sep 17 00:00:00 2001
-Date: Mon, 10 Jun 2024 10:03:08 +0200
-Subject: [PATCH 3/5] ARM: dts: stm32: add ethernet1/2 RMII pins for
- STM32MP13F-DK board
-
-Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board.
-ethernet1: RMII with crystal.
-ethernet2: RMII without crystal.
-Add analog gpio pin configuration ("sleep") to manage power mode on
-stm32mp13.
-
----
- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 98 +++++++++++++++++++++
- 1 file changed, 98 insertions(+)
-
---- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
-+++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
-@@ -13,6 +13,104 @@
- };
- };
-
-+ eth1_rgmii_pins_a: eth1-rgmii-0 {
-+ pins1 {
-+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
-+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
-+ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
-+ <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */
-+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
-+ <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */
-+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
-+ <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
-+ bias-disable;
-+ drive-push-pull;
-+ slew-rate = <2>;
-+ };
-+
-+ pins2 {
-+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
-+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
-+ <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
-+ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
-+ <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
-+ <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
-+ bias-disable;
-+ };
-+
-+ };
-+
-+ eth1_rmii_pins_a: eth1-rmii-0 {
-+ pins1 {
-+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */
-+ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */
-+ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */
-+ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
-+ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
-+ <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
-+ bias-disable;
-+ drive-push-pull;
-+ slew-rate = <1>;
-+ };
-+
-+ pins2 {
-+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
-+ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */
-+ <STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */
-+ bias-disable;
-+ };
-+
-+ };
-+
-+ eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 {
-+ pins1 {
-+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */
-+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */
-+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */
-+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */
-+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
-+ <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
-+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */
-+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */
-+ <STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */
-+ };
-+ };
-+
-+ eth2_rmii_pins_a: eth2-rmii-0 {
-+ pins1 {
-+ pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */
-+ <STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */
-+ <STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */
-+ <STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */
-+ <STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */
-+ <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
-+ bias-disable;
-+ drive-push-pull;
-+ slew-rate = <1>;
-+ };
-+
-+ pins2 {
-+ pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */
-+ <STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */
-+ <STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */
-+ bias-disable;
-+ };
-+ };
-+
-+ eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 {
-+ pins1 {
-+ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */
-+ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */
-+ <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */
-+ <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */
-+ <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
-+ <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
-+ <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */
-+ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */
-+ <STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */
-+ };
-+ };
-+
- i2c1_pins_a: i2c1-0 {
- pins {
- pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
+++ /dev/null
-From fcf6ca2da4650d0a7a9cd62c8c72341860931159 Mon Sep 17 00:00:00 2001
-Date: Mon, 10 Jun 2024 10:03:07 +0200
-Subject: [PATCH 4/5] ARM: dts: stm32: add ethernet1 and ethernet2 support on
- stm32mp13
-
-Both instances ethernet based on GMAC SNPS IP on stm32mp13.
-GMAC IP version is SNPS 4.20.
-
----
- arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++
- arch/arm/boot/dts/st/stm32mp133.dtsi | 31 +++++++++++++++++++++++
- 2 files changed, 69 insertions(+)
-
---- a/arch/arm/boot/dts/st/stm32mp131.dtsi
-+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
-@@ -883,6 +883,12 @@
- ts_cal2: calib@5e {
- reg = <0x5e 0x2>;
- };
-+ ethernet_mac1_address: mac1@e4 {
-+ reg = <0xe4 0x6>;
-+ };
-+ ethernet_mac2_address: mac2@ea {
-+ reg = <0xea 0x6>;
-+ };
- };
-
- etzpc: bus@5c007000 {
-@@ -1409,6 +1415,38 @@
- status = "disabled";
- };
-
-+ ethernet1: ethernet@5800a000 {
-+ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
-+ reg = <0x5800a000 0x2000>;
-+ reg-names = "stmmaceth";
-+ interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
-+ <&exti 68 1>;
-+ interrupt-names = "macirq", "eth_wake_irq";
-+ clock-names = "stmmaceth",
-+ "mac-clk-tx",
-+ "mac-clk-rx",
-+ "ethstp",
-+ "eth-ck";
-+ clocks = <&rcc ETH1MAC>,
-+ <&rcc ETH1TX>,
-+ <&rcc ETH1RX>,
-+ <&rcc ETH1STP>,
-+ <&rcc ETH1CK_K>;
-+ st,syscon = <&syscfg 0x4 0xff0000>;
-+ snps,mixed-burst;
-+ snps,pbl = <2>;
-+ snps,axi-config = <&stmmac_axi_config_1>;
-+ snps,tso;
-+ access-controllers = <&etzpc 48>;
-+ status = "disabled";
-+
-+ stmmac_axi_config_1: stmmac-axi-config {
-+ snps,blen = <0 0 0 0 16 8 4>;
-+ snps,rd_osr_lmt = <0x7>;
-+ snps,wr_osr_lmt = <0x7>;
-+ };
-+ };
-+
- usbphyc: usbphyc@5a006000 {
- #address-cells = <1>;
- #size-cells = <0>;
---- a/arch/arm/boot/dts/st/stm32mp133.dtsi
-+++ b/arch/arm/boot/dts/st/stm32mp133.dtsi
-@@ -68,4 +68,35 @@
- };
- };
- };
-+
-+ ethernet2: ethernet@5800e000 {
-+ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
-+ reg = <0x5800e000 0x2000>;
-+ reg-names = "stmmaceth";
-+ interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "macirq";
-+ clock-names = "stmmaceth",
-+ "mac-clk-tx",
-+ "mac-clk-rx",
-+ "ethstp",
-+ "eth-ck";
-+ clocks = <&rcc ETH2MAC>,
-+ <&rcc ETH2TX>,
-+ <&rcc ETH2RX>,
-+ <&rcc ETH2STP>,
-+ <&rcc ETH2CK_K>;
-+ st,syscon = <&syscfg 0x4 0xff000000>;
-+ snps,mixed-burst;
-+ snps,pbl = <2>;
-+ snps,axi-config = <&stmmac_axi_config_2>;
-+ snps,tso;
-+ access-controllers = <&etzpc 49>;
-+ status = "disabled";
-+
-+ stmmac_axi_config_2: stmmac-axi-config {
-+ snps,blen = <0 0 0 0 16 8 4>;
-+ snps,rd_osr_lmt = <0x7>;
-+ snps,wr_osr_lmt = <0x7>;
-+ };
-+ };
- };
+++ /dev/null
-From b255afeeb33efaa974b1b2454b1f58252d783b67 Mon Sep 17 00:00:00 2001
-Date: Mon, 10 Jun 2024 10:03:09 +0200
-Subject: [PATCH 5/5] ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
-
-Ethernet1: RMII with crystal
-Ethernet2: RMII with no cristal, need "phy-supply" property to work,
-today this property was managed by Ethernet glue, but should be present
-and managed in PHY node. So I will push second Ethernet in next step.
-
-PHYs used are SMSC (LAN8742A)
-
----
- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
---- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
-+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
-@@ -19,6 +19,7 @@
- compatible = "st,stm32mp135f-dk", "st,stm32mp135";
-
- aliases {
-+ ethernet0 = ðernet1;
- serial0 = &uart4;
- serial1 = &usart1;
- serial2 = &uart8;
-@@ -92,6 +93,28 @@
- };
- };
- };
-+
-+ðernet1 {
-+ status = "okay";
-+ pinctrl-0 = <ð1_rmii_pins_a>;
-+ pinctrl-1 = <ð1_rmii_sleep_pins_a>;
-+ pinctrl-names = "default", "sleep";
-+ phy-mode = "rmii";
-+ phy-handle = <&phy0_eth1>;
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "snps,dwmac-mdio";
-+
-+ phy0_eth1: ethernet-phy@0 {
-+ compatible = "ethernet-phy-id0007.c131";
-+ reg = <0>;
-+ reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>;
-+ wakeup-source;
-+ };
-+ };
-+};
-
- &i2c1 {
- pinctrl-names = "default", "sleep";
--- /dev/null
+From d788961c5b25d9d822c4230bfbc536a6736b91ff Mon Sep 17 00:00:00 2001
+Date: Fri, 5 Jan 2024 14:04:03 +0100
+Subject: [PATCH 1/5] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x
+ boards
+
+ETZPC is a firewall controller. Put all peripherals filtered by the
+ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for
+backward compatibility.
+
+---
+ arch/arm/boot/dts/st/stm32mp131.dtsi | 1020 +++++++++++++------------
+ arch/arm/boot/dts/st/stm32mp133.dtsi | 50 +-
+ arch/arm/boot/dts/st/stm32mp13xc.dtsi | 18 +-
+ arch/arm/boot/dts/st/stm32mp13xf.dtsi | 18 +-
+ 4 files changed, 569 insertions(+), 537 deletions(-)
+
+--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
+@@ -745,340 +745,6 @@
+ dma-channels = <16>;
+ };
+
+- adc_2: adc@48004000 {
+- compatible = "st,stm32mp13-adc-core";
+- reg = <0x48004000 0x400>;
+- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc ADC2>, <&rcc ADC2_K>;
+- clock-names = "bus", "adc";
+- interrupt-controller;
+- #interrupt-cells = <1>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- status = "disabled";
+-
+- adc2: adc@0 {
+- compatible = "st,stm32mp13-adc";
+- #io-channel-cells = <1>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- reg = <0x0>;
+- interrupt-parent = <&adc_2>;
+- interrupts = <0>;
+- dmas = <&dmamux1 10 0x400 0x80000001>;
+- dma-names = "rx";
+- status = "disabled";
+-
+- channel@13 {
+- reg = <13>;
+- label = "vrefint";
+- };
+- channel@14 {
+- reg = <14>;
+- label = "vddcore";
+- };
+- channel@16 {
+- reg = <16>;
+- label = "vddcpu";
+- };
+- channel@17 {
+- reg = <17>;
+- label = "vddq_ddr";
+- };
+- };
+- };
+-
+- usbotg_hs: usb@49000000 {
+- compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+- reg = <0x49000000 0x40000>;
+- clocks = <&rcc USBO_K>;
+- clock-names = "otg";
+- resets = <&rcc USBO_R>;
+- reset-names = "dwc2";
+- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+- g-rx-fifo-size = <512>;
+- g-np-tx-fifo-size = <32>;
+- g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+- dr_mode = "otg";
+- otg-rev = <0x200>;
+- usb33d-supply = <&scmi_usb33>;
+- status = "disabled";
+- };
+-
+- usart1: serial@4c000000 {
+- compatible = "st,stm32h7-uart";
+- reg = <0x4c000000 0x400>;
+- interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc USART1_K>;
+- resets = <&rcc USART1_R>;
+- wakeup-source;
+- dmas = <&dmamux1 41 0x400 0x5>,
+- <&dmamux1 42 0x400 0x1>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
+-
+- usart2: serial@4c001000 {
+- compatible = "st,stm32h7-uart";
+- reg = <0x4c001000 0x400>;
+- interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc USART2_K>;
+- resets = <&rcc USART2_R>;
+- wakeup-source;
+- dmas = <&dmamux1 43 0x400 0x5>,
+- <&dmamux1 44 0x400 0x1>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
+-
+- i2s4: audio-controller@4c002000 {
+- compatible = "st,stm32h7-i2s";
+- reg = <0x4c002000 0x400>;
+- #sound-dai-cells = <0>;
+- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmamux1 83 0x400 0x01>,
+- <&dmamux1 84 0x400 0x01>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
+-
+- spi4: spi@4c002000 {
+- compatible = "st,stm32h7-spi";
+- reg = <0x4c002000 0x400>;
+- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SPI4_K>;
+- resets = <&rcc SPI4_R>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- dmas = <&dmamux1 83 0x400 0x01>,
+- <&dmamux1 84 0x400 0x01>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
+-
+- spi5: spi@4c003000 {
+- compatible = "st,stm32h7-spi";
+- reg = <0x4c003000 0x400>;
+- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SPI5_K>;
+- resets = <&rcc SPI5_R>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- dmas = <&dmamux1 85 0x400 0x01>,
+- <&dmamux1 86 0x400 0x01>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
+-
+- i2c3: i2c@4c004000 {
+- compatible = "st,stm32mp13-i2c";
+- reg = <0x4c004000 0x400>;
+- interrupt-names = "event", "error";
+- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc I2C3_K>;
+- resets = <&rcc I2C3_R>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- dmas = <&dmamux1 73 0x400 0x1>,
+- <&dmamux1 74 0x400 0x1>;
+- dma-names = "rx", "tx";
+- st,syscfg-fmp = <&syscfg 0x4 0x4>;
+- i2c-analog-filter;
+- status = "disabled";
+- };
+-
+- i2c4: i2c@4c005000 {
+- compatible = "st,stm32mp13-i2c";
+- reg = <0x4c005000 0x400>;
+- interrupt-names = "event", "error";
+- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc I2C4_K>;
+- resets = <&rcc I2C4_R>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- dmas = <&dmamux1 75 0x400 0x1>,
+- <&dmamux1 76 0x400 0x1>;
+- dma-names = "rx", "tx";
+- st,syscfg-fmp = <&syscfg 0x4 0x8>;
+- i2c-analog-filter;
+- status = "disabled";
+- };
+-
+- i2c5: i2c@4c006000 {
+- compatible = "st,stm32mp13-i2c";
+- reg = <0x4c006000 0x400>;
+- interrupt-names = "event", "error";
+- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc I2C5_K>;
+- resets = <&rcc I2C5_R>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- dmas = <&dmamux1 115 0x400 0x1>,
+- <&dmamux1 116 0x400 0x1>;
+- dma-names = "rx", "tx";
+- st,syscfg-fmp = <&syscfg 0x4 0x10>;
+- i2c-analog-filter;
+- status = "disabled";
+- };
+-
+- timers12: timer@4c007000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x4c007000 0x400>;
+- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM12_K>;
+- clock-names = "int";
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- timer@11 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <11>;
+- status = "disabled";
+- };
+- };
+-
+- timers13: timer@4c008000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x4c008000 0x400>;
+- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM13_K>;
+- clock-names = "int";
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- timer@12 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <12>;
+- status = "disabled";
+- };
+- };
+-
+- timers14: timer@4c009000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x4c009000 0x400>;
+- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM14_K>;
+- clock-names = "int";
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- timer@13 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <13>;
+- status = "disabled";
+- };
+- };
+-
+- timers15: timer@4c00a000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x4c00a000 0x400>;
+- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM15_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 105 0x400 0x1>,
+- <&dmamux1 106 0x400 0x1>,
+- <&dmamux1 107 0x400 0x1>,
+- <&dmamux1 108 0x400 0x1>;
+- dma-names = "ch1", "up", "trig", "com";
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- timer@14 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <14>;
+- status = "disabled";
+- };
+- };
+-
+- timers16: timer@4c00b000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x4c00b000 0x400>;
+- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM16_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 109 0x400 0x1>,
+- <&dmamux1 110 0x400 0x1>;
+- dma-names = "ch1", "up";
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- timer@15 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <15>;
+- status = "disabled";
+- };
+- };
+-
+- timers17: timer@4c00c000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x4c00c000 0x400>;
+- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM17_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 111 0x400 0x1>,
+- <&dmamux1 112 0x400 0x1>;
+- dma-names = "ch1", "up";
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- timer@16 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <16>;
+- status = "disabled";
+- };
+- };
+-
+ rcc: rcc@50000000 {
+ compatible = "st,stm32mp13-rcc", "syscon";
+ reg = <0x50000000 0x1000>;
+@@ -1105,69 +771,6 @@
+ clocks = <&rcc SYSCFG>;
+ };
+
+- lptimer2: timer@50021000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-lptimer";
+- reg = <0x50021000 0x400>;
+- interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc LPTIM2_K>;
+- clock-names = "mux";
+- wakeup-source;
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm-lp";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- trigger@1 {
+- compatible = "st,stm32-lptimer-trigger";
+- reg = <1>;
+- status = "disabled";
+- };
+-
+- counter {
+- compatible = "st,stm32-lptimer-counter";
+- status = "disabled";
+- };
+-
+- timer {
+- compatible = "st,stm32-lptimer-timer";
+- status = "disabled";
+- };
+- };
+-
+- lptimer3: timer@50022000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-lptimer";
+- reg = <0x50022000 0x400>;
+- interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc LPTIM3_K>;
+- clock-names = "mux";
+- wakeup-source;
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm-lp";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- trigger@2 {
+- compatible = "st,stm32-lptimer-trigger";
+- reg = <2>;
+- status = "disabled";
+- };
+-
+- timer {
+- compatible = "st,stm32-lptimer-timer";
+- status = "disabled";
+- };
+- };
+-
+ lptimer4: timer@50023000 {
+ compatible = "st,stm32-lptimer";
+ reg = <0x50023000 0x400>;
+@@ -1220,79 +823,10 @@
+ dma-requests = <48>;
+ };
+
+- fmc: memory-controller@58002000 {
+- compatible = "st,stm32mp1-fmc2-ebi";
+- reg = <0x58002000 0x1000>;
+- ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+- <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+- <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+- <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+- <4 0 0x80000000 0x10000000>; /* NAND */
+- #address-cells = <2>;
+- #size-cells = <1>;
+- clocks = <&rcc FMC_K>;
+- resets = <&rcc FMC_R>;
+- status = "disabled";
+-
+- nand-controller@4,0 {
+- compatible = "st,stm32mp1-fmc2-nfc";
+- reg = <4 0x00000000 0x1000>,
+- <4 0x08010000 0x1000>,
+- <4 0x08020000 0x1000>,
+- <4 0x01000000 0x1000>,
+- <4 0x09010000 0x1000>,
+- <4 0x09020000 0x1000>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
+- <&mdma 24 0x2 0x12000a08 0x0 0x0>,
+- <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
+- dma-names = "tx", "rx", "ecc";
+- status = "disabled";
+- };
+- };
+-
+- qspi: spi@58003000 {
+- compatible = "st,stm32f469-qspi";
+- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+- reg-names = "qspi", "qspi_mm";
+- #address-cells = <1>;
+- #size-cells = <0>;
+- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
+- <&mdma 26 0x2 0x10100008 0x0 0x0>;
+- dma-names = "tx", "rx";
+- clocks = <&rcc QSPI_K>;
+- resets = <&rcc QSPI_R>;
+- status = "disabled";
+- };
+-
+- sdmmc1: mmc@58005000 {
+- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+- arm,primecell-periphid = <0x20253180>;
+- reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SDMMC1_K>;
+- clock-names = "apb_pclk";
+- resets = <&rcc SDMMC1_R>;
+- cap-sd-highspeed;
+- cap-mmc-highspeed;
+- max-frequency = <130000000>;
+- status = "disabled";
+- };
+-
+- sdmmc2: mmc@58007000 {
+- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+- arm,primecell-periphid = <0x20253180>;
+- reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
+- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SDMMC2_K>;
+- clock-names = "apb_pclk";
+- resets = <&rcc SDMMC2_R>;
+- cap-sd-highspeed;
+- cap-mmc-highspeed;
+- max-frequency = <130000000>;
++ crc1: crc@58009000 {
++ compatible = "st,stm32f7-crc";
++ reg = <0x58009000 0x400>;
++ clocks = <&rcc CRC1>;
+ status = "disabled";
+ };
+
+@@ -1323,29 +857,6 @@
+ status = "disabled";
+ };
+
+- usbphyc: usbphyc@5a006000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- #clock-cells = <0>;
+- compatible = "st,stm32mp1-usbphyc";
+- reg = <0x5a006000 0x1000>;
+- clocks = <&rcc USBPHY_K>;
+- resets = <&rcc USBPHY_R>;
+- vdda1v1-supply = <&scmi_reg11>;
+- vdda1v8-supply = <&scmi_reg18>;
+- status = "disabled";
+-
+- usbphyc_port0: usb-phy@0 {
+- #phy-cells = <0>;
+- reg = <0>;
+- };
+-
+- usbphyc_port1: usb-phy@1 {
+- #phy-cells = <1>;
+- reg = <1>;
+- };
+- };
+-
+ rtc: rtc@5c004000 {
+ compatible = "st,stm32mp1-rtc";
+ reg = <0x5c004000 0x400>;
+@@ -1374,6 +885,529 @@
+ };
+ };
+
++ etzpc: bus@5c007000 {
++ compatible = "simple-bus";
++ reg = <0x5c007000 0x400>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ adc_2: adc@48004000 {
++ compatible = "st,stm32mp13-adc-core";
++ reg = <0x48004000 0x400>;
++ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc ADC2>, <&rcc ADC2_K>;
++ clock-names = "bus", "adc";
++ interrupt-controller;
++ #interrupt-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ adc2: adc@0 {
++ compatible = "st,stm32mp13-adc";
++ #io-channel-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>;
++ interrupt-parent = <&adc_2>;
++ interrupts = <0>;
++ dmas = <&dmamux1 10 0x400 0x80000001>;
++ dma-names = "rx";
++ status = "disabled";
++
++ channel@13 {
++ reg = <13>;
++ label = "vrefint";
++ };
++ channel@14 {
++ reg = <14>;
++ label = "vddcore";
++ };
++ channel@16 {
++ reg = <16>;
++ label = "vddcpu";
++ };
++ channel@17 {
++ reg = <17>;
++ label = "vddq_ddr";
++ };
++ };
++ };
++
++ usbotg_hs: usb@49000000 {
++ compatible = "st,stm32mp15-hsotg", "snps,dwc2";
++ reg = <0x49000000 0x40000>;
++ clocks = <&rcc USBO_K>;
++ clock-names = "otg";
++ resets = <&rcc USBO_R>;
++ reset-names = "dwc2";
++ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
++ g-rx-fifo-size = <512>;
++ g-np-tx-fifo-size = <32>;
++ g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
++ dr_mode = "otg";
++ otg-rev = <0x200>;
++ usb33d-supply = <&scmi_usb33>;
++ status = "disabled";
++ };
++
++ usart1: serial@4c000000 {
++ compatible = "st,stm32h7-uart";
++ reg = <0x4c000000 0x400>;
++ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc USART1_K>;
++ resets = <&rcc USART1_R>;
++ wakeup-source;
++ dmas = <&dmamux1 41 0x400 0x5>,
++ <&dmamux1 42 0x400 0x1>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ usart2: serial@4c001000 {
++ compatible = "st,stm32h7-uart";
++ reg = <0x4c001000 0x400>;
++ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc USART2_K>;
++ resets = <&rcc USART2_R>;
++ wakeup-source;
++ dmas = <&dmamux1 43 0x400 0x5>,
++ <&dmamux1 44 0x400 0x1>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ i2s4: audio-controller@4c002000 {
++ compatible = "st,stm32h7-i2s";
++ reg = <0x4c002000 0x400>;
++ #sound-dai-cells = <0>;
++ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmamux1 83 0x400 0x01>,
++ <&dmamux1 84 0x400 0x01>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ spi4: spi@4c002000 {
++ compatible = "st,stm32h7-spi";
++ reg = <0x4c002000 0x400>;
++ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SPI4_K>;
++ resets = <&rcc SPI4_R>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ dmas = <&dmamux1 83 0x400 0x01>,
++ <&dmamux1 84 0x400 0x01>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ spi5: spi@4c003000 {
++ compatible = "st,stm32h7-spi";
++ reg = <0x4c003000 0x400>;
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SPI5_K>;
++ resets = <&rcc SPI5_R>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ dmas = <&dmamux1 85 0x400 0x01>,
++ <&dmamux1 86 0x400 0x01>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ i2c3: i2c@4c004000 {
++ compatible = "st,stm32mp13-i2c";
++ reg = <0x4c004000 0x400>;
++ interrupt-names = "event", "error";
++ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc I2C3_K>;
++ resets = <&rcc I2C3_R>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ dmas = <&dmamux1 73 0x400 0x1>,
++ <&dmamux1 74 0x400 0x1>;
++ dma-names = "rx", "tx";
++ st,syscfg-fmp = <&syscfg 0x4 0x4>;
++ i2c-analog-filter;
++ status = "disabled";
++ };
++
++ i2c4: i2c@4c005000 {
++ compatible = "st,stm32mp13-i2c";
++ reg = <0x4c005000 0x400>;
++ interrupt-names = "event", "error";
++ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc I2C4_K>;
++ resets = <&rcc I2C4_R>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ dmas = <&dmamux1 75 0x400 0x1>,
++ <&dmamux1 76 0x400 0x1>;
++ dma-names = "rx", "tx";
++ st,syscfg-fmp = <&syscfg 0x4 0x8>;
++ i2c-analog-filter;
++ status = "disabled";
++ };
++
++ i2c5: i2c@4c006000 {
++ compatible = "st,stm32mp13-i2c";
++ reg = <0x4c006000 0x400>;
++ interrupt-names = "event", "error";
++ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc I2C5_K>;
++ resets = <&rcc I2C5_R>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ dmas = <&dmamux1 115 0x400 0x1>,
++ <&dmamux1 116 0x400 0x1>;
++ dma-names = "rx", "tx";
++ st,syscfg-fmp = <&syscfg 0x4 0x10>;
++ i2c-analog-filter;
++ status = "disabled";
++ };
++
++ timers12: timer@4c007000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x4c007000 0x400>;
++ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM12_K>;
++ clock-names = "int";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ timer@11 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <11>;
++ status = "disabled";
++ };
++ };
++
++ timers13: timer@4c008000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x4c008000 0x400>;
++ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM13_K>;
++ clock-names = "int";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ timer@12 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <12>;
++ status = "disabled";
++ };
++ };
++
++ timers14: timer@4c009000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x4c009000 0x400>;
++ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM14_K>;
++ clock-names = "int";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ timer@13 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <13>;
++ status = "disabled";
++ };
++ };
++
++ timers15: timer@4c00a000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x4c00a000 0x400>;
++ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM15_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 105 0x400 0x1>,
++ <&dmamux1 106 0x400 0x1>,
++ <&dmamux1 107 0x400 0x1>,
++ <&dmamux1 108 0x400 0x1>;
++ dma-names = "ch1", "up", "trig", "com";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ timer@14 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <14>;
++ status = "disabled";
++ };
++ };
++
++ timers16: timer@4c00b000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x4c00b000 0x400>;
++ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM16_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 109 0x400 0x1>,
++ <&dmamux1 110 0x400 0x1>;
++ dma-names = "ch1", "up";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ timer@15 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <15>;
++ status = "disabled";
++ };
++ };
++
++ timers17: timer@4c00c000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x4c00c000 0x400>;
++ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM17_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 111 0x400 0x1>,
++ <&dmamux1 112 0x400 0x1>;
++ dma-names = "ch1", "up";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ timer@16 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <16>;
++ status = "disabled";
++ };
++ };
++
++ lptimer2: timer@50021000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-lptimer";
++ reg = <0x50021000 0x400>;
++ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc LPTIM2_K>;
++ clock-names = "mux";
++ wakeup-source;
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm-lp";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ trigger@1 {
++ compatible = "st,stm32-lptimer-trigger";
++ reg = <1>;
++ status = "disabled";
++ };
++
++ counter {
++ compatible = "st,stm32-lptimer-counter";
++ status = "disabled";
++ };
++
++ timer {
++ compatible = "st,stm32-lptimer-timer";
++ status = "disabled";
++ };
++ };
++
++ lptimer3: timer@50022000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-lptimer";
++ reg = <0x50022000 0x400>;
++ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc LPTIM3_K>;
++ clock-names = "mux";
++ wakeup-source;
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm-lp";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ trigger@2 {
++ compatible = "st,stm32-lptimer-trigger";
++ reg = <2>;
++ status = "disabled";
++ };
++
++ timer {
++ compatible = "st,stm32-lptimer-timer";
++ status = "disabled";
++ };
++ };
++
++ hash: hash@54003000 {
++ compatible = "st,stm32mp13-hash";
++ reg = <0x54003000 0x400>;
++ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc HASH1>;
++ resets = <&rcc HASH1_R>;
++ dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>;
++ dma-names = "in";
++ status = "disabled";
++ };
++
++ rng: rng@54004000 {
++ compatible = "st,stm32mp13-rng";
++ reg = <0x54004000 0x400>;
++ clocks = <&rcc RNG1_K>;
++ resets = <&rcc RNG1_R>;
++ status = "disabled";
++ };
++
++ fmc: memory-controller@58002000 {
++ compatible = "st,stm32mp1-fmc2-ebi";
++ reg = <0x58002000 0x1000>;
++ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
++ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
++ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
++ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
++ <4 0 0x80000000 0x10000000>; /* NAND */
++ #address-cells = <2>;
++ #size-cells = <1>;
++ clocks = <&rcc FMC_K>;
++ resets = <&rcc FMC_R>;
++ status = "disabled";
++
++ nand-controller@4,0 {
++ compatible = "st,stm32mp1-fmc2-nfc";
++ reg = <4 0x00000000 0x1000>,
++ <4 0x08010000 0x1000>,
++ <4 0x08020000 0x1000>,
++ <4 0x01000000 0x1000>,
++ <4 0x09010000 0x1000>,
++ <4 0x09020000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
++ <&mdma 24 0x2 0x12000a08 0x0 0x0>,
++ <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
++ dma-names = "tx", "rx", "ecc";
++ status = "disabled";
++ };
++ };
++
++ qspi: spi@58003000 {
++ compatible = "st,stm32f469-qspi";
++ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
++ reg-names = "qspi", "qspi_mm";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
++ <&mdma 26 0x2 0x10100008 0x0 0x0>;
++ dma-names = "tx", "rx";
++ clocks = <&rcc QSPI_K>;
++ resets = <&rcc QSPI_R>;
++ status = "disabled";
++ };
++
++ sdmmc1: mmc@58005000 {
++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
++ arm,primecell-periphid = <0x20253180>;
++ reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
++ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SDMMC1_K>;
++ clock-names = "apb_pclk";
++ resets = <&rcc SDMMC1_R>;
++ cap-sd-highspeed;
++ cap-mmc-highspeed;
++ max-frequency = <130000000>;
++ status = "disabled";
++ };
++
++ sdmmc2: mmc@58007000 {
++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
++ arm,primecell-periphid = <0x20253180>;
++ reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
++ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SDMMC2_K>;
++ clock-names = "apb_pclk";
++ resets = <&rcc SDMMC2_R>;
++ cap-sd-highspeed;
++ cap-mmc-highspeed;
++ max-frequency = <130000000>;
++ status = "disabled";
++ };
++
++ usbphyc: usbphyc@5a006000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ #clock-cells = <0>;
++ compatible = "st,stm32mp1-usbphyc";
++ reg = <0x5a006000 0x1000>;
++ clocks = <&rcc USBPHY_K>;
++ resets = <&rcc USBPHY_R>;
++ vdda1v1-supply = <&scmi_reg11>;
++ vdda1v8-supply = <&scmi_reg18>;
++ status = "disabled";
++
++ usbphyc_port0: usb-phy@0 {
++ #phy-cells = <0>;
++ reg = <0>;
++ };
++
++ usbphyc_port1: usb-phy@1 {
++ #phy-cells = <1>;
++ reg = <1>;
++ };
++ };
++ };
++
+ /*
+ * Break node order to solve dependency probe issue between
+ * pinctrl and exti.
+--- a/arch/arm/boot/dts/st/stm32mp133.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp133.dtsi
+@@ -33,35 +33,37 @@
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+ status = "disabled";
+ };
++ };
++};
++
++&etzpc {
++ adc_1: adc@48003000 {
++ compatible = "st,stm32mp13-adc-core";
++ reg = <0x48003000 0x400>;
++ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc ADC1>, <&rcc ADC1_K>;
++ clock-names = "bus", "adc";
++ interrupt-controller;
++ #interrupt-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
+
+- adc_1: adc@48003000 {
+- compatible = "st,stm32mp13-adc-core";
+- reg = <0x48003000 0x400>;
+- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc ADC1>, <&rcc ADC1_K>;
+- clock-names = "bus", "adc";
+- interrupt-controller;
+- #interrupt-cells = <1>;
++ adc1: adc@0 {
++ compatible = "st,stm32mp13-adc";
++ #io-channel-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
++ reg = <0x0>;
++ interrupt-parent = <&adc_1>;
++ interrupts = <0>;
++ dmas = <&dmamux1 9 0x400 0x80000001>;
++ dma-names = "rx";
+ status = "disabled";
+
+- adc1: adc@0 {
+- compatible = "st,stm32mp13-adc";
+- #io-channel-cells = <1>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- reg = <0x0>;
+- interrupt-parent = <&adc_1>;
+- interrupts = <0>;
+- dmas = <&dmamux1 9 0x400 0x80000001>;
+- dma-names = "rx";
+- status = "disabled";
+-
+- channel@18 {
+- reg = <18>;
+- label = "vrefint";
+- };
++ channel@18 {
++ reg = <18>;
++ label = "vrefint";
+ };
+ };
+ };
+--- a/arch/arm/boot/dts/st/stm32mp13xc.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp13xc.dtsi
+@@ -4,15 +4,13 @@
+ */
+
+-/ {
+- soc {
+- cryp: crypto@54002000 {
+- compatible = "st,stm32mp1-cryp";
+- reg = <0x54002000 0x400>;
+- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc CRYP1>;
+- resets = <&rcc CRYP1_R>;
+- status = "disabled";
+- };
++&etzpc {
++ cryp: crypto@54002000 {
++ compatible = "st,stm32mp1-cryp";
++ reg = <0x54002000 0x400>;
++ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc CRYP1>;
++ resets = <&rcc CRYP1_R>;
++ status = "disabled";
+ };
+ };
+--- a/arch/arm/boot/dts/st/stm32mp13xf.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp13xf.dtsi
+@@ -4,15 +4,13 @@
+ */
+
+-/ {
+- soc {
+- cryp: crypto@54002000 {
+- compatible = "st,stm32mp1-cryp";
+- reg = <0x54002000 0x400>;
+- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc CRYP1>;
+- resets = <&rcc CRYP1_R>;
+- status = "disabled";
+- };
++&etzpc {
++ cryp: crypto@54002000 {
++ compatible = "st,stm32mp1-cryp";
++ reg = <0x54002000 0x400>;
++ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc CRYP1>;
++ resets = <&rcc CRYP1_R>;
++ status = "disabled";
+ };
+ };
+++ /dev/null
-From 1bcfbfd7c9aa716f61a01682345a1b329f6a6e66 Mon Sep 17 00:00:00 2001
-Date: Wed, 8 Nov 2023 15:16:37 +0100
-Subject: [PATCH] mmc: mmci: stm32: add SDIO in-band interrupt mode
-
-Add the support of SDIO in-band interrupt mode for STM32 and Ux500
-variants.
-It allows the SD I/O card to interrupt the host on SDMMC_D1 data line.
-It is not enabled by default on Ux500 variant as this is unstable and
-Ux500 users should use out-of-band IRQs.
-
----
- drivers/mmc/host/mmci.c | 69 +++++++++++++++++++++++++++++++++++++++--
- drivers/mmc/host/mmci.h | 2 ++
- 2 files changed, 69 insertions(+), 2 deletions(-)
-
---- a/drivers/mmc/host/mmci.c
-+++ b/drivers/mmc/host/mmci.c
-@@ -272,6 +272,7 @@ static struct variant_data variant_stm32
- .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
- .stm32_idmabsize_mask = GENMASK(12, 5),
- .stm32_idmabsize_align = BIT(5),
-+ .supports_sdio_irq = true,
- .busy_timeout = true,
- .busy_detect = true,
- .busy_detect_flag = MCI_STM32_BUSYD0,
-@@ -299,6 +300,7 @@ static struct variant_data variant_stm32
- .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
- .stm32_idmabsize_mask = GENMASK(16, 5),
- .stm32_idmabsize_align = BIT(5),
-+ .supports_sdio_irq = true,
- .dma_lli = true,
- .busy_timeout = true,
- .busy_detect = true,
-@@ -327,6 +329,7 @@ static struct variant_data variant_stm32
- .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
- .stm32_idmabsize_mask = GENMASK(16, 6),
- .stm32_idmabsize_align = BIT(6),
-+ .supports_sdio_irq = true,
- .dma_lli = true,
- .busy_timeout = true,
- .busy_detect = true,
-@@ -420,8 +423,9 @@ void mmci_write_pwrreg(struct mmci_host
- */
- static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
- {
-- /* Keep busy mode in DPSM if enabled */
-- datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
-+ /* Keep busy mode in DPSM and SDIO mask if enabled */
-+ datactrl |= host->datactrl_reg & (host->variant->busy_dpsm_flag |
-+ host->variant->datactrl_mask_sdio);
-
- if (host->datactrl_reg != datactrl) {
- host->datactrl_reg = datactrl;
-@@ -1761,6 +1765,25 @@ static irqreturn_t mmci_pio_irq(int irq,
- return IRQ_HANDLED;
- }
-
-+static void mmci_write_sdio_irq_bit(struct mmci_host *host, int enable)
-+{
-+ void __iomem *base = host->base;
-+ u32 mask = readl_relaxed(base + MMCIMASK0);
-+
-+ if (enable)
-+ writel_relaxed(mask | MCI_ST_SDIOITMASK, base + MMCIMASK0);
-+ else
-+ writel_relaxed(mask & ~MCI_ST_SDIOITMASK, base + MMCIMASK0);
-+}
-+
-+static void mmci_signal_sdio_irq(struct mmci_host *host, u32 status)
-+{
-+ if (status & MCI_ST_SDIOIT) {
-+ mmci_write_sdio_irq_bit(host, 0);
-+ sdio_signal_irq(host->mmc);
-+ }
-+}
-+
- /*
- * Handle completion of command and data transfers.
- */
-@@ -1805,6 +1828,9 @@ static irqreturn_t mmci_irq(int irq, voi
- mmci_data_irq(host, host->data, status);
- }
-
-+ if (host->variant->supports_sdio_irq)
-+ mmci_signal_sdio_irq(host, status);
-+
- /*
- * Busy detection has been handled by mmci_cmd_irq() above.
- * Clear the status bit to prevent polling in IRQ context.
-@@ -2041,6 +2067,35 @@ static int mmci_sig_volt_switch(struct m
- return ret;
- }
-
-+static void mmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
-+{
-+ struct mmci_host *host = mmc_priv(mmc);
-+ unsigned long flags;
-+
-+ if (enable)
-+ /* Keep the SDIO mode bit if SDIO irqs are enabled */
-+ pm_runtime_get_sync(mmc_dev(mmc));
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+ mmci_write_sdio_irq_bit(host, enable);
-+ spin_unlock_irqrestore(&host->lock, flags);
-+
-+ if (!enable) {
-+ pm_runtime_mark_last_busy(mmc_dev(mmc));
-+ pm_runtime_put_autosuspend(mmc_dev(mmc));
-+ }
-+}
-+
-+static void mmci_ack_sdio_irq(struct mmc_host *mmc)
-+{
-+ struct mmci_host *host = mmc_priv(mmc);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&host->lock, flags);
-+ mmci_write_sdio_irq_bit(host, 1);
-+ spin_unlock_irqrestore(&host->lock, flags);
-+}
-+
- static struct mmc_host_ops mmci_ops = {
- .request = mmci_request,
- .pre_req = mmci_pre_request,
-@@ -2316,6 +2371,16 @@ static int mmci_probe(struct amba_device
- mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
- }
-
-+ if (variant->supports_sdio_irq && host->mmc->caps & MMC_CAP_SDIO_IRQ) {
-+ mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
-+
-+ mmci_ops.enable_sdio_irq = mmci_enable_sdio_irq;
-+ mmci_ops.ack_sdio_irq = mmci_ack_sdio_irq;
-+
-+ mmci_write_datactrlreg(host,
-+ host->variant->datactrl_mask_sdio);
-+ }
-+
- /* Variants with mandatory busy timeout in HW needs R1B responses. */
- if (variant->busy_timeout)
- mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
---- a/drivers/mmc/host/mmci.h
-+++ b/drivers/mmc/host/mmci.h
-@@ -331,6 +331,7 @@ enum mmci_busy_state {
- * register.
- * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
- * @dma_lli: true if variant has dma link list feature.
-+ * @supports_sdio_irq: allow SD I/O card to interrupt the host
- * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
- */
- struct variant_data {
-@@ -376,6 +377,7 @@ struct variant_data {
- u32 start_err;
- u32 opendrain;
- u8 dma_lli:1;
-+ bool supports_sdio_irq;
- u32 stm32_idmabsize_mask;
- u32 stm32_idmabsize_align;
- void (*init)(struct mmci_host *host);
--- /dev/null
+From 21ca3d7c59595d76237faebeff4f6a979cf7ae82 Mon Sep 17 00:00:00 2001
+Date: Fri, 5 Apr 2024 13:45:24 +0200
+Subject: [PATCH 2/5] ARM: dts: stm32: put ETZPC as an access controller for
+ STM32MP13x boards
+
+Reference ETZPC as an access-control-provider.
+
+For more information on which peripheral is securable or supports MCU
+isolation, please read the STM32MP13 reference manual
+
+---
+ arch/arm/boot/dts/st/stm32mp131.dtsi | 28 ++++++++++++++++++++++++++-
+ arch/arm/boot/dts/st/stm32mp133.dtsi | 1 +
+ arch/arm/boot/dts/st/stm32mp13xc.dtsi | 1 +
+ arch/arm/boot/dts/st/stm32mp13xf.dtsi | 1 +
+ 4 files changed, 30 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
+@@ -886,10 +886,11 @@
+ };
+
+ etzpc: bus@5c007000 {
+- compatible = "simple-bus";
++ compatible = "st,stm32-etzpc", "simple-bus";
+ reg = <0x5c007000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
++ #access-controller-cells = <1>;
+ ranges;
+
+ adc_2: adc@48004000 {
+@@ -902,6 +903,7 @@
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
++ access-controllers = <&etzpc 33>;
+ status = "disabled";
+
+ adc2: adc@0 {
+@@ -949,6 +951,7 @@
+ dr_mode = "otg";
+ otg-rev = <0x200>;
+ usb33d-supply = <&scmi_usb33>;
++ access-controllers = <&etzpc 34>;
+ status = "disabled";
+ };
+
+@@ -962,6 +965,7 @@
+ dmas = <&dmamux1 41 0x400 0x5>,
+ <&dmamux1 42 0x400 0x1>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 16>;
+ status = "disabled";
+ };
+
+@@ -975,6 +979,7 @@
+ dmas = <&dmamux1 43 0x400 0x5>,
+ <&dmamux1 44 0x400 0x1>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 17>;
+ status = "disabled";
+ };
+
+@@ -986,6 +991,7 @@
+ dmas = <&dmamux1 83 0x400 0x01>,
+ <&dmamux1 84 0x400 0x01>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 13>;
+ status = "disabled";
+ };
+
+@@ -1000,6 +1006,7 @@
+ dmas = <&dmamux1 83 0x400 0x01>,
+ <&dmamux1 84 0x400 0x01>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 18>;
+ status = "disabled";
+ };
+
+@@ -1014,6 +1021,7 @@
+ dmas = <&dmamux1 85 0x400 0x01>,
+ <&dmamux1 86 0x400 0x01>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 19>;
+ status = "disabled";
+ };
+
+@@ -1032,6 +1040,7 @@
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x4>;
+ i2c-analog-filter;
++ access-controllers = <&etzpc 20>;
+ status = "disabled";
+ };
+
+@@ -1050,6 +1059,7 @@
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x8>;
+ i2c-analog-filter;
++ access-controllers = <&etzpc 21>;
+ status = "disabled";
+ };
+
+@@ -1068,6 +1078,7 @@
+ dma-names = "rx", "tx";
+ st,syscfg-fmp = <&syscfg 0x4 0x10>;
+ i2c-analog-filter;
++ access-controllers = <&etzpc 22>;
+ status = "disabled";
+ };
+
+@@ -1080,6 +1091,7 @@
+ interrupt-names = "global";
+ clocks = <&rcc TIM12_K>;
+ clock-names = "int";
++ access-controllers = <&etzpc 23>;
+ status = "disabled";
+
+ pwm {
+@@ -1104,6 +1116,7 @@
+ interrupt-names = "global";
+ clocks = <&rcc TIM13_K>;
+ clock-names = "int";
++ access-controllers = <&etzpc 24>;
+ status = "disabled";
+
+ pwm {
+@@ -1128,6 +1141,7 @@
+ interrupt-names = "global";
+ clocks = <&rcc TIM14_K>;
+ clock-names = "int";
++ access-controllers = <&etzpc 25>;
+ status = "disabled";
+
+ pwm {
+@@ -1157,6 +1171,7 @@
+ <&dmamux1 107 0x400 0x1>,
+ <&dmamux1 108 0x400 0x1>;
+ dma-names = "ch1", "up", "trig", "com";
++ access-controllers = <&etzpc 26>;
+ status = "disabled";
+
+ pwm {
+@@ -1184,6 +1199,7 @@
+ dmas = <&dmamux1 109 0x400 0x1>,
+ <&dmamux1 110 0x400 0x1>;
+ dma-names = "ch1", "up";
++ access-controllers = <&etzpc 27>;
+ status = "disabled";
+
+ pwm {
+@@ -1211,6 +1227,7 @@
+ dmas = <&dmamux1 111 0x400 0x1>,
+ <&dmamux1 112 0x400 0x1>;
+ dma-names = "ch1", "up";
++ access-controllers = <&etzpc 28>;
+ status = "disabled";
+
+ pwm {
+@@ -1235,6 +1252,7 @@
+ clocks = <&rcc LPTIM2_K>;
+ clock-names = "mux";
+ wakeup-source;
++ access-controllers = <&etzpc 1>;
+ status = "disabled";
+
+ pwm {
+@@ -1269,6 +1287,7 @@
+ clocks = <&rcc LPTIM3_K>;
+ clock-names = "mux";
+ wakeup-source;
++ access-controllers = <&etzpc 2>;
+ status = "disabled";
+
+ pwm {
+@@ -1297,6 +1316,7 @@
+ resets = <&rcc HASH1_R>;
+ dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>;
+ dma-names = "in";
++ access-controllers = <&etzpc 41>;
+ status = "disabled";
+ };
+
+@@ -1305,6 +1325,7 @@
+ reg = <0x54004000 0x400>;
+ clocks = <&rcc RNG1_K>;
+ resets = <&rcc RNG1_R>;
++ access-controllers = <&etzpc 40>;
+ status = "disabled";
+ };
+
+@@ -1320,6 +1341,7 @@
+ #size-cells = <1>;
+ clocks = <&rcc FMC_K>;
+ resets = <&rcc FMC_R>;
++ access-controllers = <&etzpc 54>;
+ status = "disabled";
+
+ nand-controller@4,0 {
+@@ -1353,6 +1375,7 @@
+ dma-names = "tx", "rx";
+ clocks = <&rcc QSPI_K>;
+ resets = <&rcc QSPI_R>;
++ access-controllers = <&etzpc 55>;
+ status = "disabled";
+ };
+
+@@ -1367,6 +1390,7 @@
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <130000000>;
++ access-controllers = <&etzpc 50>;
+ status = "disabled";
+ };
+
+@@ -1381,6 +1405,7 @@
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <130000000>;
++ access-controllers = <&etzpc 51>;
+ status = "disabled";
+ };
+
+@@ -1394,6 +1419,7 @@
+ resets = <&rcc USBPHY_R>;
+ vdda1v1-supply = <&scmi_reg11>;
+ vdda1v8-supply = <&scmi_reg18>;
++ access-controllers = <&etzpc 5>;
+ status = "disabled";
+
+ usbphyc_port0: usb-phy@0 {
+--- a/arch/arm/boot/dts/st/stm32mp133.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp133.dtsi
+@@ -47,6 +47,7 @@
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
++ access-controllers = <&etzpc 32>;
+ status = "disabled";
+
+ adc1: adc@0 {
+--- a/arch/arm/boot/dts/st/stm32mp13xc.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp13xc.dtsi
+@@ -11,6 +11,7 @@
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
++ access-controllers = <&etzpc 42>;
+ status = "disabled";
+ };
+ };
+--- a/arch/arm/boot/dts/st/stm32mp13xf.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp13xf.dtsi
+@@ -11,6 +11,7 @@
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
++ access-controllers = <&etzpc 42>;
+ status = "disabled";
+ };
+ };
--- /dev/null
+From b1468a44e0c0f43a06e027efeff4183b3aee0cf7 Mon Sep 17 00:00:00 2001
+Date: Mon, 10 Jun 2024 10:03:08 +0200
+Subject: [PATCH 3/5] ARM: dts: stm32: add ethernet1/2 RMII pins for
+ STM32MP13F-DK board
+
+Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board.
+ethernet1: RMII with crystal.
+ethernet2: RMII without crystal.
+Add analog gpio pin configuration ("sleep") to manage power mode on
+stm32mp13.
+
+---
+ arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 98 +++++++++++++++++++++
+ 1 file changed, 98 insertions(+)
+
+--- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
+@@ -13,6 +13,104 @@
+ };
+ };
+
++ eth1_rgmii_pins_a: eth1-rgmii-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
++ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
++ <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
++ <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */
++ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
++ <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */
++ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
++ <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <2>;
++ };
++
++ pins2 {
++ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
++ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
++ <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
++ <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
++ <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
++ <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
++ bias-disable;
++ };
++
++ };
++
++ eth1_rmii_pins_a: eth1-rmii-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */
++ <STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */
++ <STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */
++ <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
++ <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
++ <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++
++ pins2 {
++ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
++ <STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */
++ <STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */
++ bias-disable;
++ };
++
++ };
++
++ eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */
++ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */
++ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */
++ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */
++ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
++ <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
++ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */
++ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */
++ <STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */
++ };
++ };
++
++ eth2_rmii_pins_a: eth2-rmii-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */
++ <STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */
++ <STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */
++ <STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */
++ <STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */
++ <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
++ bias-disable;
++ drive-push-pull;
++ slew-rate = <1>;
++ };
++
++ pins2 {
++ pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */
++ <STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */
++ <STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */
++ bias-disable;
++ };
++ };
++
++ eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 {
++ pins1 {
++ pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */
++ <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */
++ <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */
++ <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */
++ <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
++ <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
++ <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */
++ <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */
++ <STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */
++ };
++ };
++
+ i2c1_pins_a: i2c1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
--- /dev/null
+From fcf6ca2da4650d0a7a9cd62c8c72341860931159 Mon Sep 17 00:00:00 2001
+Date: Mon, 10 Jun 2024 10:03:07 +0200
+Subject: [PATCH 4/5] ARM: dts: stm32: add ethernet1 and ethernet2 support on
+ stm32mp13
+
+Both instances ethernet based on GMAC SNPS IP on stm32mp13.
+GMAC IP version is SNPS 4.20.
+
+---
+ arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++
+ arch/arm/boot/dts/st/stm32mp133.dtsi | 31 +++++++++++++++++++++++
+ 2 files changed, 69 insertions(+)
+
+--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
+@@ -883,6 +883,12 @@
+ ts_cal2: calib@5e {
+ reg = <0x5e 0x2>;
+ };
++ ethernet_mac1_address: mac1@e4 {
++ reg = <0xe4 0x6>;
++ };
++ ethernet_mac2_address: mac2@ea {
++ reg = <0xea 0x6>;
++ };
+ };
+
+ etzpc: bus@5c007000 {
+@@ -1409,6 +1415,38 @@
+ status = "disabled";
+ };
+
++ ethernet1: ethernet@5800a000 {
++ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
++ reg = <0x5800a000 0x2000>;
++ reg-names = "stmmaceth";
++ interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
++ <&exti 68 1>;
++ interrupt-names = "macirq", "eth_wake_irq";
++ clock-names = "stmmaceth",
++ "mac-clk-tx",
++ "mac-clk-rx",
++ "ethstp",
++ "eth-ck";
++ clocks = <&rcc ETH1MAC>,
++ <&rcc ETH1TX>,
++ <&rcc ETH1RX>,
++ <&rcc ETH1STP>,
++ <&rcc ETH1CK_K>;
++ st,syscon = <&syscfg 0x4 0xff0000>;
++ snps,mixed-burst;
++ snps,pbl = <2>;
++ snps,axi-config = <&stmmac_axi_config_1>;
++ snps,tso;
++ access-controllers = <&etzpc 48>;
++ status = "disabled";
++
++ stmmac_axi_config_1: stmmac-axi-config {
++ snps,blen = <0 0 0 0 16 8 4>;
++ snps,rd_osr_lmt = <0x7>;
++ snps,wr_osr_lmt = <0x7>;
++ };
++ };
++
+ usbphyc: usbphyc@5a006000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+--- a/arch/arm/boot/dts/st/stm32mp133.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp133.dtsi
+@@ -68,4 +68,35 @@
+ };
+ };
+ };
++
++ ethernet2: ethernet@5800e000 {
++ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
++ reg = <0x5800e000 0x2000>;
++ reg-names = "stmmaceth";
++ interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq";
++ clock-names = "stmmaceth",
++ "mac-clk-tx",
++ "mac-clk-rx",
++ "ethstp",
++ "eth-ck";
++ clocks = <&rcc ETH2MAC>,
++ <&rcc ETH2TX>,
++ <&rcc ETH2RX>,
++ <&rcc ETH2STP>,
++ <&rcc ETH2CK_K>;
++ st,syscon = <&syscfg 0x4 0xff000000>;
++ snps,mixed-burst;
++ snps,pbl = <2>;
++ snps,axi-config = <&stmmac_axi_config_2>;
++ snps,tso;
++ access-controllers = <&etzpc 49>;
++ status = "disabled";
++
++ stmmac_axi_config_2: stmmac-axi-config {
++ snps,blen = <0 0 0 0 16 8 4>;
++ snps,rd_osr_lmt = <0x7>;
++ snps,wr_osr_lmt = <0x7>;
++ };
++ };
+ };
--- /dev/null
+From b255afeeb33efaa974b1b2454b1f58252d783b67 Mon Sep 17 00:00:00 2001
+Date: Mon, 10 Jun 2024 10:03:09 +0200
+Subject: [PATCH 5/5] ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board
+
+Ethernet1: RMII with crystal
+Ethernet2: RMII with no cristal, need "phy-supply" property to work,
+today this property was managed by Ethernet glue, but should be present
+and managed in PHY node. So I will push second Ethernet in next step.
+
+PHYs used are SMSC (LAN8742A)
+
+---
+ arch/arm/boot/dts/st/stm32mp135f-dk.dts | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
++++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+@@ -19,6 +19,7 @@
+ compatible = "st,stm32mp135f-dk", "st,stm32mp135";
+
+ aliases {
++ ethernet0 = ðernet1;
+ serial0 = &uart4;
+ serial1 = &usart1;
+ serial2 = &uart8;
+@@ -92,6 +93,28 @@
+ };
+ };
+ };
++
++ðernet1 {
++ status = "okay";
++ pinctrl-0 = <ð1_rmii_pins_a>;
++ pinctrl-1 = <ð1_rmii_sleep_pins_a>;
++ pinctrl-names = "default", "sleep";
++ phy-mode = "rmii";
++ phy-handle = <&phy0_eth1>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "snps,dwmac-mdio";
++
++ phy0_eth1: ethernet-phy@0 {
++ compatible = "ethernet-phy-id0007.c131";
++ reg = <0>;
++ reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>;
++ wakeup-source;
++ };
++ };
++};
+
+ &i2c1 {
+ pinctrl-names = "default", "sleep";
--- /dev/null
+From d6b0d7a941c4fc9241d9cca66db5d8ff9d81cc8b Mon Sep 17 00:00:00 2001
+Date: Tue, 27 Aug 2024 16:04:47 +0200
+Subject: [PATCH] ARM: dts: stm32: rtc, add pin to provide LSCO on stm32mp15
+
+Declare pin for LSCO in stm32-pinctrl provider node to reserve this pin
+for RTC OUT2_RMP, in stm32mp15-pinctrl.dtsi.
+
+---
+ arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi
+@@ -1467,6 +1467,13 @@
+ };
+ };
+
++ /omit-if-no-ref/
++ rtc_rsvd_pins_a: rtc-rsvd-0 {
++ pins {
++ pinmux = <STM32_PINMUX('I', 8, ANALOG)>; /* RTC_OUT2_RMP */
++ };
++ };
++
+ sai2a_pins_a: sai2a-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
--- /dev/null
+From c24e7ae60d3e97799998466a4220ef6ffa0e4c94 Mon Sep 17 00:00:00 2001
+Date: Tue, 27 Aug 2024 16:04:49 +0200
+Subject: [PATCH] ARM: dts: stm32: rtc, add LSCO to WLAN/BT module on
+ stm32mp157c-dk2
+
+On stm32mp157c-dk2 board, WLAN/BT module LPO_IN pin is wired to
+RTC OUT2_RMP pin.
+
+Provide a pinctrl configuration to enable LSCO on OUT2_RMP.
+
+---
+ arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
++++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
+@@ -84,6 +84,16 @@
+ };
+ };
+
++&rtc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtc_rsvd_pins_a>;
++
++ rtc_lsco_pins_a: rtc-lsco-0 {
++ pins = "out2_rmp";
++ function = "lsco";
++ };
++};
++
+ &usart2 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_c>;
--- /dev/null
+From 315fe7667c03c1f853e1a7038c28f23621a44a3d Mon Sep 17 00:00:00 2001
+Date: Tue, 27 Aug 2024 16:04:51 +0200
+Subject: [PATCH] ARM: dts: stm32: add support of WLAN/BT on stm32mp157c-dk2
+
+Add support of WLAN/BT Murata Type 1DX module:
+- usart2 is used for Bluetooth interface
+- sdmmc2 is used for WLAN (sdio) interface
+
+---
+ arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 41 +++++++++++++++++++++++-
+ 1 file changed, 40 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
++++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
+@@ -24,6 +24,11 @@
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
++
++ wifi_pwrseq: wifi-pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
++ };
+ };
+
+ &cryp1 {
+@@ -94,10 +99,44 @@
+ };
+ };
+
++/* Wifi */
++&sdmmc2 {
++ pinctrl-names = "default", "opendrain", "sleep";
++ pinctrl-0 = <&sdmmc2_b4_pins_a>;
++ pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
++ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
++ non-removable;
++ cap-sdio-irq;
++ st,neg-edge;
++ bus-width = <4>;
++ vmmc-supply = <&v3v3>;
++ mmc-pwrseq = <&wifi_pwrseq>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "okay";
++
++ brcmf: bcrmf@1 {
++ reg = <1>;
++ compatible = "brcm,bcm4329-fmac";
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtc_lsco_pins_a>;
++ };
++};
++
++/* Bluetooth */
+ &usart2 {
+ pinctrl-names = "default", "sleep", "idle";
+ pinctrl-0 = <&usart2_pins_c>;
+ pinctrl-1 = <&usart2_sleep_pins_c>;
+ pinctrl-2 = <&usart2_idle_pins_c>;
+- status = "disabled";
++ uart-has-rtscts;
++ status = "okay";
++
++ bluetooth {
++ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
++ compatible = "brcm,bcm43438-bt";
++ max-speed = <3000000>;
++ vbat-supply = <&v3v3>;
++ vddio-supply = <&v3v3>;
++ };
+ };
--- /dev/null
+From ad95b569993b0735a58b08c00cd4131fa5e83376 Mon Sep 17 00:00:00 2001
+Date: Fri, 5 Jan 2024 14:04:01 +0100
+Subject: [PATCH] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x
+ boards
+
+ETZPC is a firewall controller. Put all peripherals filtered by the
+ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for
+backward compatibility.
+
+---
+ arch/arm/boot/dts/st/stm32mp151.dtsi | 2676 +++++++++++++------------
+ arch/arm/boot/dts/st/stm32mp153.dtsi | 50 +-
+ arch/arm/boot/dts/st/stm32mp15xc.dtsi | 18 +-
+ 3 files changed, 1375 insertions(+), 1369 deletions(-)
+
+--- a/arch/arm/boot/dts/st/stm32mp151.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
+@@ -123,1541 +123,1549 @@
+ interrupt-parent = <&intc>;
+ ranges;
+
+- timers2: timer@40000000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x40000000 0x400>;
+- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM2_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 18 0x400 0x1>,
+- <&dmamux1 19 0x400 0x1>,
+- <&dmamux1 20 0x400 0x1>,
+- <&dmamux1 21 0x400 0x1>,
+- <&dmamux1 22 0x400 0x1>;
+- dma-names = "ch1", "ch2", "ch3", "ch4", "up";
++ ipcc: mailbox@4c001000 {
++ compatible = "st,stm32mp1-ipcc";
++ #mbox-cells = <1>;
++ reg = <0x4c001000 0x400>;
++ st,proc-id = <0>;
++ interrupts-extended =
++ <&exti 61 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "rx", "tx";
++ clocks = <&rcc IPCC>;
++ wakeup-source;
+ status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- timer@1 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <1>;
+- status = "disabled";
+- };
+-
+- counter {
+- compatible = "st,stm32-timer-counter";
+- status = "disabled";
+- };
+ };
+
+- timers3: timer@40001000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x40001000 0x400>;
+- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM3_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 23 0x400 0x1>,
+- <&dmamux1 24 0x400 0x1>,
+- <&dmamux1 25 0x400 0x1>,
+- <&dmamux1 26 0x400 0x1>,
+- <&dmamux1 27 0x400 0x1>,
+- <&dmamux1 28 0x400 0x1>;
+- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- timer@2 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <2>;
+- status = "disabled";
+- };
+-
+- counter {
+- compatible = "st,stm32-timer-counter";
+- status = "disabled";
+- };
++ rcc: rcc@50000000 {
++ compatible = "st,stm32mp1-rcc", "syscon";
++ reg = <0x50000000 0x1000>;
++ #clock-cells = <1>;
++ #reset-cells = <1>;
+ };
+
+- timers4: timer@40002000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x40002000 0x400>;
+- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM4_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 29 0x400 0x1>,
+- <&dmamux1 30 0x400 0x1>,
+- <&dmamux1 31 0x400 0x1>,
+- <&dmamux1 32 0x400 0x1>;
+- dma-names = "ch1", "ch2", "ch3", "ch4";
+- status = "disabled";
++ pwr_regulators: pwr@50001000 {
++ compatible = "st,stm32mp1,pwr-reg";
++ reg = <0x50001000 0x10>;
+
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
++ reg11: reg11 {
++ regulator-name = "reg11";
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1100000>;
+ };
+
+- timer@3 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <3>;
+- status = "disabled";
++ reg18: reg18 {
++ regulator-name = "reg18";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
+ };
+
+- counter {
+- compatible = "st,stm32-timer-counter";
+- status = "disabled";
++ usb33: usb33 {
++ regulator-name = "usb33";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
+ };
+ };
+
+- timers5: timer@40003000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x40003000 0x400>;
+- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM5_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 55 0x400 0x1>,
+- <&dmamux1 56 0x400 0x1>,
+- <&dmamux1 57 0x400 0x1>,
+- <&dmamux1 58 0x400 0x1>,
+- <&dmamux1 59 0x400 0x1>,
+- <&dmamux1 60 0x400 0x1>;
+- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- timer@4 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <4>;
+- status = "disabled";
+- };
+-
+- counter {
+- compatible = "st,stm32-timer-counter";
+- status = "disabled";
+- };
++ pwr_mcu: pwr_mcu@50001014 {
++ compatible = "st,stm32mp151-pwr-mcu", "syscon";
++ reg = <0x50001014 0x4>;
+ };
+
+- timers6: timer@40004000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x40004000 0x400>;
+- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM6_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 69 0x400 0x1>;
+- dma-names = "up";
+- status = "disabled";
+-
+- timer@5 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <5>;
+- status = "disabled";
+- };
++ exti: interrupt-controller@5000d000 {
++ compatible = "st,stm32mp1-exti", "syscon";
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x5000d000 0x400>;
+ };
+
+- timers7: timer@40005000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x40005000 0x400>;
+- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM7_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 70 0x400 0x1>;
+- dma-names = "up";
+- status = "disabled";
+-
+- timer@6 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <6>;
+- status = "disabled";
+- };
++ syscfg: syscon@50020000 {
++ compatible = "st,stm32mp157-syscfg", "syscon";
++ reg = <0x50020000 0x400>;
++ clocks = <&rcc SYSCFG>;
+ };
+
+- timers12: timer@40006000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x40006000 0x400>;
+- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM12_K>;
+- clock-names = "int";
++ dts: thermal@50028000 {
++ compatible = "st,stm32-thermal";
++ reg = <0x50028000 0x100>;
++ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc TMPSENS>;
++ clock-names = "pclk";
++ #thermal-sensor-cells = <0>;
+ status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- timer@11 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <11>;
+- status = "disabled";
+- };
+ };
+
+- timers13: timer@40007000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x40007000 0x400>;
+- interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM13_K>;
+- clock-names = "int";
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- timer@12 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <12>;
+- status = "disabled";
+- };
++ mdma1: dma-controller@58000000 {
++ compatible = "st,stm32h7-mdma";
++ reg = <0x58000000 0x1000>;
++ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc MDMA>;
++ resets = <&rcc MDMA_R>;
++ #dma-cells = <5>;
++ dma-channels = <32>;
++ dma-requests = <48>;
+ };
+
+- timers14: timer@40008000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x40008000 0x400>;
+- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM14_K>;
+- clock-names = "int";
++ sdmmc1: mmc@58005000 {
++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
++ arm,primecell-periphid = <0x00253180>;
++ reg = <0x58005000 0x1000>;
++ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SDMMC1_K>;
++ clock-names = "apb_pclk";
++ resets = <&rcc SDMMC1_R>;
++ cap-sd-highspeed;
++ cap-mmc-highspeed;
++ max-frequency = <120000000>;
+ status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- timer@13 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <13>;
+- status = "disabled";
+- };
+ };
+
+- lptimer1: timer@40009000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-lptimer";
+- reg = <0x40009000 0x400>;
+- interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc LPTIM1_K>;
+- clock-names = "mux";
+- wakeup-source;
++ sdmmc2: mmc@58007000 {
++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
++ arm,primecell-periphid = <0x00253180>;
++ reg = <0x58007000 0x1000>;
++ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SDMMC2_K>;
++ clock-names = "apb_pclk";
++ resets = <&rcc SDMMC2_R>;
++ cap-sd-highspeed;
++ cap-mmc-highspeed;
++ max-frequency = <120000000>;
+ status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm-lp";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+-
+- trigger@0 {
+- compatible = "st,stm32-lptimer-trigger";
+- reg = <0>;
+- status = "disabled";
+- };
+-
+- counter {
+- compatible = "st,stm32-lptimer-counter";
+- status = "disabled";
+- };
+ };
+
+- spi2: spi@4000b000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32h7-spi";
+- reg = <0x4000b000 0x400>;
+- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SPI2_K>;
+- resets = <&rcc SPI2_R>;
+- dmas = <&dmamux1 39 0x400 0x05>,
+- <&dmamux1 40 0x400 0x05>;
+- dma-names = "rx", "tx";
++ crc1: crc@58009000 {
++ compatible = "st,stm32f7-crc";
++ reg = <0x58009000 0x400>;
++ clocks = <&rcc CRC1>;
+ status = "disabled";
+ };
+
+- i2s2: audio-controller@4000b000 {
+- compatible = "st,stm32h7-i2s";
+- #sound-dai-cells = <0>;
+- reg = <0x4000b000 0x400>;
+- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmamux1 39 0x400 0x01>,
+- <&dmamux1 40 0x400 0x01>;
+- dma-names = "rx", "tx";
++ usbh_ohci: usb@5800c000 {
++ compatible = "generic-ohci";
++ reg = <0x5800c000 0x1000>;
++ clocks = <&usbphyc>, <&rcc USBH>;
++ resets = <&rcc USBH_R>;
++ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+- spi3: spi@4000c000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32h7-spi";
+- reg = <0x4000c000 0x400>;
+- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SPI3_K>;
+- resets = <&rcc SPI3_R>;
+- dmas = <&dmamux1 61 0x400 0x05>,
+- <&dmamux1 62 0x400 0x05>;
+- dma-names = "rx", "tx";
++ usbh_ehci: usb@5800d000 {
++ compatible = "generic-ehci";
++ reg = <0x5800d000 0x1000>;
++ clocks = <&usbphyc>, <&rcc USBH>;
++ resets = <&rcc USBH_R>;
++ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++ companion = <&usbh_ohci>;
+ status = "disabled";
+ };
+
+- i2s3: audio-controller@4000c000 {
+- compatible = "st,stm32h7-i2s";
+- #sound-dai-cells = <0>;
+- reg = <0x4000c000 0x400>;
+- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmamux1 61 0x400 0x01>,
+- <&dmamux1 62 0x400 0x01>;
+- dma-names = "rx", "tx";
++ ltdc: display-controller@5a001000 {
++ compatible = "st,stm32-ltdc";
++ reg = <0x5a001000 0x400>;
++ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc LTDC_PX>;
++ clock-names = "lcd";
++ resets = <&rcc LTDC_R>;
+ status = "disabled";
+ };
+
+- spdifrx: audio-controller@4000d000 {
+- compatible = "st,stm32h7-spdifrx";
+- #sound-dai-cells = <0>;
+- reg = <0x4000d000 0x400>;
+- clocks = <&rcc SPDIF_K>;
+- clock-names = "kclk";
+- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmamux1 93 0x400 0x01>,
+- <&dmamux1 94 0x400 0x01>;
+- dma-names = "rx", "rx-ctrl";
++ iwdg2: watchdog@5a002000 {
++ compatible = "st,stm32mp1-iwdg";
++ reg = <0x5a002000 0x400>;
++ clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
++ clock-names = "pclk", "lsi";
+ status = "disabled";
+ };
+
+- usart2: serial@4000e000 {
+- compatible = "st,stm32h7-uart";
+- reg = <0x4000e000 0x400>;
+- interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc USART2_K>;
+- wakeup-source;
+- dmas = <&dmamux1 43 0x400 0x15>,
+- <&dmamux1 44 0x400 0x11>;
+- dma-names = "rx", "tx";
++ usbphyc: usbphyc@5a006000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ #clock-cells = <0>;
++ compatible = "st,stm32mp1-usbphyc";
++ reg = <0x5a006000 0x1000>;
++ clocks = <&rcc USBPHY_K>;
++ resets = <&rcc USBPHY_R>;
++ vdda1v1-supply = <®11>;
++ vdda1v8-supply = <®18>;
+ status = "disabled";
+- };
+
+- usart3: serial@4000f000 {
+- compatible = "st,stm32h7-uart";
+- reg = <0x4000f000 0x400>;
+- interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc USART3_K>;
+- wakeup-source;
+- dmas = <&dmamux1 45 0x400 0x15>,
+- <&dmamux1 46 0x400 0x11>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
++ usbphyc_port0: usb-phy@0 {
++ #phy-cells = <0>;
++ reg = <0>;
++ };
+
+- uart4: serial@40010000 {
+- compatible = "st,stm32h7-uart";
+- reg = <0x40010000 0x400>;
+- interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc UART4_K>;
+- wakeup-source;
+- dmas = <&dmamux1 63 0x400 0x15>,
+- <&dmamux1 64 0x400 0x11>;
+- dma-names = "rx", "tx";
+- status = "disabled";
++ usbphyc_port1: usb-phy@1 {
++ #phy-cells = <1>;
++ reg = <1>;
++ };
+ };
+
+- uart5: serial@40011000 {
+- compatible = "st,stm32h7-uart";
+- reg = <0x40011000 0x400>;
+- interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc UART5_K>;
+- wakeup-source;
+- dmas = <&dmamux1 65 0x400 0x15>,
+- <&dmamux1 66 0x400 0x11>;
+- dma-names = "rx", "tx";
++ rtc: rtc@5c004000 {
++ compatible = "st,stm32mp1-rtc";
++ reg = <0x5c004000 0x400>;
++ clocks = <&rcc RTCAPB>, <&rcc RTC>;
++ clock-names = "pclk", "rtc_ck";
++ interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+- i2c1: i2c@40012000 {
+- compatible = "st,stm32mp15-i2c";
+- reg = <0x40012000 0x400>;
+- interrupt-names = "event", "error";
+- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc I2C1_K>;
+- resets = <&rcc I2C1_R>;
++ bsec: efuse@5c005000 {
++ compatible = "st,stm32mp15-bsec";
++ reg = <0x5c005000 0x400>;
+ #address-cells = <1>;
+- #size-cells = <0>;
+- st,syscfg-fmp = <&syscfg 0x4 0x1>;
+- wakeup-source;
+- i2c-analog-filter;
+- status = "disabled";
++ #size-cells = <1>;
++ part_number_otp: part-number-otp@4 {
++ reg = <0x4 0x1>;
++ };
++ vrefint: vrefin-cal@52 {
++ reg = <0x52 0x2>;
++ };
++ ts_cal1: calib@5c {
++ reg = <0x5c 0x2>;
++ };
++ ts_cal2: calib@5e {
++ reg = <0x5e 0x2>;
++ };
+ };
+
+- i2c2: i2c@40013000 {
+- compatible = "st,stm32mp15-i2c";
+- reg = <0x40013000 0x400>;
+- interrupt-names = "event", "error";
+- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc I2C2_K>;
+- resets = <&rcc I2C2_R>;
++ etzpc: bus@5c007000 {
++ compatible = "simple-bus";
++ reg = <0x5c007000 0x400>;
+ #address-cells = <1>;
+- #size-cells = <0>;
+- st,syscfg-fmp = <&syscfg 0x4 0x2>;
+- wakeup-source;
+- i2c-analog-filter;
+- status = "disabled";
+- };
++ #size-cells = <1>;
++ ranges;
+
+- i2c3: i2c@40014000 {
+- compatible = "st,stm32mp15-i2c";
+- reg = <0x40014000 0x400>;
+- interrupt-names = "event", "error";
+- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc I2C3_K>;
+- resets = <&rcc I2C3_R>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- st,syscfg-fmp = <&syscfg 0x4 0x4>;
+- wakeup-source;
+- i2c-analog-filter;
+- status = "disabled";
+- };
++ timers2: timer@40000000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x40000000 0x400>;
++ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM2_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 18 0x400 0x1>,
++ <&dmamux1 19 0x400 0x1>,
++ <&dmamux1 20 0x400 0x1>,
++ <&dmamux1 21 0x400 0x1>,
++ <&dmamux1 22 0x400 0x1>;
++ dma-names = "ch1", "ch2", "ch3", "ch4", "up";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
+
+- i2c5: i2c@40015000 {
+- compatible = "st,stm32mp15-i2c";
+- reg = <0x40015000 0x400>;
+- interrupt-names = "event", "error";
+- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc I2C5_K>;
+- resets = <&rcc I2C5_R>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- st,syscfg-fmp = <&syscfg 0x4 0x10>;
+- wakeup-source;
+- i2c-analog-filter;
+- status = "disabled";
+- };
++ timer@1 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <1>;
++ status = "disabled";
++ };
+
+- cec: cec@40016000 {
+- compatible = "st,stm32-cec";
+- reg = <0x40016000 0x400>;
+- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc CEC_K>, <&rcc CEC>;
+- clock-names = "cec", "hdmi-cec";
+- status = "disabled";
+- };
++ counter {
++ compatible = "st,stm32-timer-counter";
++ status = "disabled";
++ };
++ };
+
+- dac: dac@40017000 {
+- compatible = "st,stm32h7-dac-core";
+- reg = <0x40017000 0x400>;
+- clocks = <&rcc DAC12>;
+- clock-names = "pclk";
+- #address-cells = <1>;
+- #size-cells = <0>;
+- status = "disabled";
++ timers3: timer@40001000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x40001000 0x400>;
++ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM3_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 23 0x400 0x1>,
++ <&dmamux1 24 0x400 0x1>,
++ <&dmamux1 25 0x400 0x1>,
++ <&dmamux1 26 0x400 0x1>,
++ <&dmamux1 27 0x400 0x1>,
++ <&dmamux1 28 0x400 0x1>;
++ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
+
+- dac1: dac@1 {
+- compatible = "st,stm32-dac";
+- #io-channel-cells = <1>;
+- reg = <1>;
+- status = "disabled";
++ timer@2 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <2>;
++ status = "disabled";
++ };
++
++ counter {
++ compatible = "st,stm32-timer-counter";
++ status = "disabled";
++ };
+ };
+
+- dac2: dac@2 {
+- compatible = "st,stm32-dac";
+- #io-channel-cells = <1>;
+- reg = <2>;
+- status = "disabled";
++ timers4: timer@40002000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x40002000 0x400>;
++ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM4_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 29 0x400 0x1>,
++ <&dmamux1 30 0x400 0x1>,
++ <&dmamux1 31 0x400 0x1>,
++ <&dmamux1 32 0x400 0x1>;
++ dma-names = "ch1", "ch2", "ch3", "ch4";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ timer@3 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <3>;
++ status = "disabled";
++ };
++
++ counter {
++ compatible = "st,stm32-timer-counter";
++ status = "disabled";
++ };
+ };
+- };
+
+- uart7: serial@40018000 {
+- compatible = "st,stm32h7-uart";
+- reg = <0x40018000 0x400>;
+- interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc UART7_K>;
+- wakeup-source;
+- dmas = <&dmamux1 79 0x400 0x15>,
+- <&dmamux1 80 0x400 0x11>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
++ timers5: timer@40003000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x40003000 0x400>;
++ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM5_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 55 0x400 0x1>,
++ <&dmamux1 56 0x400 0x1>,
++ <&dmamux1 57 0x400 0x1>,
++ <&dmamux1 58 0x400 0x1>,
++ <&dmamux1 59 0x400 0x1>,
++ <&dmamux1 60 0x400 0x1>;
++ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
+
+- uart8: serial@40019000 {
+- compatible = "st,stm32h7-uart";
+- reg = <0x40019000 0x400>;
+- interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc UART8_K>;
+- wakeup-source;
+- dmas = <&dmamux1 81 0x400 0x15>,
+- <&dmamux1 82 0x400 0x11>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
++ timer@4 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <4>;
++ status = "disabled";
++ };
+
+- timers1: timer@44000000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x44000000 0x400>;
+- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "brk", "up", "trg-com", "cc";
+- clocks = <&rcc TIM1_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 11 0x400 0x1>,
+- <&dmamux1 12 0x400 0x1>,
+- <&dmamux1 13 0x400 0x1>,
+- <&dmamux1 14 0x400 0x1>,
+- <&dmamux1 15 0x400 0x1>,
+- <&dmamux1 16 0x400 0x1>,
+- <&dmamux1 17 0x400 0x1>;
+- dma-names = "ch1", "ch2", "ch3", "ch4",
+- "up", "trig", "com";
+- status = "disabled";
++ counter {
++ compatible = "st,stm32-timer-counter";
++ status = "disabled";
++ };
++ };
+
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
++ timers6: timer@40004000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x40004000 0x400>;
++ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM6_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 69 0x400 0x1>;
++ dma-names = "up";
+ status = "disabled";
++
++ timer@5 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <5>;
++ status = "disabled";
++ };
+ };
+
+- timer@0 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <0>;
++ timers7: timer@40005000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x40005000 0x400>;
++ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM7_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 70 0x400 0x1>;
++ dma-names = "up";
+ status = "disabled";
++
++ timer@6 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <6>;
++ status = "disabled";
++ };
+ };
+
+- counter {
+- compatible = "st,stm32-timer-counter";
++ timers12: timer@40006000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x40006000 0x400>;
++ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM12_K>;
++ clock-names = "int";
+ status = "disabled";
+- };
+- };
+
+- timers8: timer@44001000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x44001000 0x400>;
+- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "brk", "up", "trg-com", "cc";
+- clocks = <&rcc TIM8_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 47 0x400 0x1>,
+- <&dmamux1 48 0x400 0x1>,
+- <&dmamux1 49 0x400 0x1>,
+- <&dmamux1 50 0x400 0x1>,
+- <&dmamux1 51 0x400 0x1>,
+- <&dmamux1 52 0x400 0x1>,
+- <&dmamux1 53 0x400 0x1>;
+- dma-names = "ch1", "ch2", "ch3", "ch4",
+- "up", "trig", "com";
+- status = "disabled";
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
+
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
++ timer@11 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <11>;
++ status = "disabled";
++ };
+ };
+
+- timer@7 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <7>;
++ timers13: timer@40007000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x40007000 0x400>;
++ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM13_K>;
++ clock-names = "int";
+ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ timer@12 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <12>;
++ status = "disabled";
++ };
+ };
+
+- counter {
+- compatible = "st,stm32-timer-counter";
++ timers14: timer@40008000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x40008000 0x400>;
++ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM14_K>;
++ clock-names = "int";
+ status = "disabled";
+- };
+- };
+
+- usart6: serial@44003000 {
+- compatible = "st,stm32h7-uart";
+- reg = <0x44003000 0x400>;
+- interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc USART6_K>;
+- wakeup-source;
+- dmas = <&dmamux1 71 0x400 0x15>,
+- <&dmamux1 72 0x400 0x11>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
+
+- spi1: spi@44004000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32h7-spi";
+- reg = <0x44004000 0x400>;
+- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SPI1_K>;
+- resets = <&rcc SPI1_R>;
+- dmas = <&dmamux1 37 0x400 0x05>,
+- <&dmamux1 38 0x400 0x05>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
++ timer@13 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <13>;
++ status = "disabled";
++ };
++ };
+
+- i2s1: audio-controller@44004000 {
+- compatible = "st,stm32h7-i2s";
+- #sound-dai-cells = <0>;
+- reg = <0x44004000 0x400>;
+- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmamux1 37 0x400 0x01>,
+- <&dmamux1 38 0x400 0x01>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
++ lptimer1: timer@40009000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-lptimer";
++ reg = <0x40009000 0x400>;
++ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc LPTIM1_K>;
++ clock-names = "mux";
++ wakeup-source;
++ status = "disabled";
+
+- spi4: spi@44005000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32h7-spi";
+- reg = <0x44005000 0x400>;
+- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SPI4_K>;
+- resets = <&rcc SPI4_R>;
+- dmas = <&dmamux1 83 0x400 0x05>,
+- <&dmamux1 84 0x400 0x05>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
++ pwm {
++ compatible = "st,stm32-pwm-lp";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
+
+- timers15: timer@44006000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x44006000 0x400>;
+- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM15_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 105 0x400 0x1>,
+- <&dmamux1 106 0x400 0x1>,
+- <&dmamux1 107 0x400 0x1>,
+- <&dmamux1 108 0x400 0x1>;
+- dma-names = "ch1", "up", "trig", "com";
+- status = "disabled";
++ trigger@0 {
++ compatible = "st,stm32-lptimer-trigger";
++ reg = <0>;
++ status = "disabled";
++ };
+
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
++ counter {
++ compatible = "st,stm32-lptimer-counter";
++ status = "disabled";
++ };
+ };
+
+- timer@14 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <14>;
++ i2s2: audio-controller@4000b000 {
++ compatible = "st,stm32h7-i2s";
++ #sound-dai-cells = <0>;
++ reg = <0x4000b000 0x400>;
++ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmamux1 39 0x400 0x01>,
++ <&dmamux1 40 0x400 0x01>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+- };
+-
+- timers16: timer@44007000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x44007000 0x400>;
+- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM16_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 109 0x400 0x1>,
+- <&dmamux1 110 0x400 0x1>;
+- dma-names = "ch1", "up";
+- status = "disabled";
+
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
+- status = "disabled";
+- };
+- timer@15 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <15>;
++ spi2: spi@4000b000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32h7-spi";
++ reg = <0x4000b000 0x400>;
++ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SPI2_K>;
++ resets = <&rcc SPI2_R>;
++ dmas = <&dmamux1 39 0x400 0x05>,
++ <&dmamux1 40 0x400 0x05>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+- };
+
+- timers17: timer@44008000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-timers";
+- reg = <0x44008000 0x400>;
+- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "global";
+- clocks = <&rcc TIM17_K>;
+- clock-names = "int";
+- dmas = <&dmamux1 111 0x400 0x1>,
+- <&dmamux1 112 0x400 0x1>;
+- dma-names = "ch1", "up";
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm";
+- #pwm-cells = <3>;
++ i2s3: audio-controller@4000c000 {
++ compatible = "st,stm32h7-i2s";
++ #sound-dai-cells = <0>;
++ reg = <0x4000c000 0x400>;
++ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmamux1 61 0x400 0x01>,
++ <&dmamux1 62 0x400 0x01>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+- timer@16 {
+- compatible = "st,stm32h7-timer-trigger";
+- reg = <16>;
++ spi3: spi@4000c000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32h7-spi";
++ reg = <0x4000c000 0x400>;
++ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SPI3_K>;
++ resets = <&rcc SPI3_R>;
++ dmas = <&dmamux1 61 0x400 0x05>,
++ <&dmamux1 62 0x400 0x05>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+- };
+
+- spi5: spi@44009000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32h7-spi";
+- reg = <0x44009000 0x400>;
+- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SPI5_K>;
+- resets = <&rcc SPI5_R>;
+- dmas = <&dmamux1 85 0x400 0x05>,
+- <&dmamux1 86 0x400 0x05>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
+-
+- sai1: sai@4400a000 {
+- compatible = "st,stm32h7-sai";
+- #address-cells = <1>;
+- #size-cells = <1>;
+- ranges = <0 0x4400a000 0x400>;
+- reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
+- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+- resets = <&rcc SAI1_R>;
+- status = "disabled";
+-
+- sai1a: audio-controller@4400a004 {
++ spdifrx: audio-controller@4000d000 {
++ compatible = "st,stm32h7-spdifrx";
+ #sound-dai-cells = <0>;
+-
+- compatible = "st,stm32-sai-sub-a";
+- reg = <0x4 0x20>;
+- clocks = <&rcc SAI1_K>;
+- clock-names = "sai_ck";
+- dmas = <&dmamux1 87 0x400 0x01>;
++ reg = <0x4000d000 0x400>;
++ clocks = <&rcc SPDIF_K>;
++ clock-names = "kclk";
++ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmamux1 93 0x400 0x01>,
++ <&dmamux1 94 0x400 0x01>;
++ dma-names = "rx", "rx-ctrl";
++ status = "disabled";
++ };
++
++ usart2: serial@4000e000 {
++ compatible = "st,stm32h7-uart";
++ reg = <0x4000e000 0x400>;
++ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc USART2_K>;
++ wakeup-source;
++ dmas = <&dmamux1 43 0x400 0x15>,
++ <&dmamux1 44 0x400 0x11>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ usart3: serial@4000f000 {
++ compatible = "st,stm32h7-uart";
++ reg = <0x4000f000 0x400>;
++ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc USART3_K>;
++ wakeup-source;
++ dmas = <&dmamux1 45 0x400 0x15>,
++ <&dmamux1 46 0x400 0x11>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ uart4: serial@40010000 {
++ compatible = "st,stm32h7-uart";
++ reg = <0x40010000 0x400>;
++ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc UART4_K>;
++ wakeup-source;
++ dmas = <&dmamux1 63 0x400 0x15>,
++ <&dmamux1 64 0x400 0x11>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ uart5: serial@40011000 {
++ compatible = "st,stm32h7-uart";
++ reg = <0x40011000 0x400>;
++ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc UART5_K>;
++ wakeup-source;
++ dmas = <&dmamux1 65 0x400 0x15>,
++ <&dmamux1 66 0x400 0x11>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ i2c1: i2c@40012000 {
++ compatible = "st,stm32mp15-i2c";
++ reg = <0x40012000 0x400>;
++ interrupt-names = "event", "error";
++ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc I2C1_K>;
++ resets = <&rcc I2C1_R>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ st,syscfg-fmp = <&syscfg 0x4 0x1>;
++ wakeup-source;
++ i2c-analog-filter;
+ status = "disabled";
+ };
+
+- sai1b: audio-controller@4400a024 {
+- #sound-dai-cells = <0>;
+- compatible = "st,stm32-sai-sub-b";
+- reg = <0x24 0x20>;
+- clocks = <&rcc SAI1_K>;
+- clock-names = "sai_ck";
+- dmas = <&dmamux1 88 0x400 0x01>;
++ i2c2: i2c@40013000 {
++ compatible = "st,stm32mp15-i2c";
++ reg = <0x40013000 0x400>;
++ interrupt-names = "event", "error";
++ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc I2C2_K>;
++ resets = <&rcc I2C2_R>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ st,syscfg-fmp = <&syscfg 0x4 0x2>;
++ wakeup-source;
++ i2c-analog-filter;
+ status = "disabled";
+ };
+- };
+
+- sai2: sai@4400b000 {
+- compatible = "st,stm32h7-sai";
+- #address-cells = <1>;
+- #size-cells = <1>;
+- ranges = <0 0x4400b000 0x400>;
+- reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+- resets = <&rcc SAI2_R>;
+- status = "disabled";
++ i2c3: i2c@40014000 {
++ compatible = "st,stm32mp15-i2c";
++ reg = <0x40014000 0x400>;
++ interrupt-names = "event", "error";
++ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc I2C3_K>;
++ resets = <&rcc I2C3_R>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ st,syscfg-fmp = <&syscfg 0x4 0x4>;
++ wakeup-source;
++ i2c-analog-filter;
++ status = "disabled";
++ };
+
+- sai2a: audio-controller@4400b004 {
+- #sound-dai-cells = <0>;
+- compatible = "st,stm32-sai-sub-a";
+- reg = <0x4 0x20>;
+- clocks = <&rcc SAI2_K>;
+- clock-names = "sai_ck";
+- dmas = <&dmamux1 89 0x400 0x01>;
++ i2c5: i2c@40015000 {
++ compatible = "st,stm32mp15-i2c";
++ reg = <0x40015000 0x400>;
++ interrupt-names = "event", "error";
++ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc I2C5_K>;
++ resets = <&rcc I2C5_R>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ st,syscfg-fmp = <&syscfg 0x4 0x10>;
++ wakeup-source;
++ i2c-analog-filter;
+ status = "disabled";
+ };
+
+- sai2b: audio-controller@4400b024 {
+- #sound-dai-cells = <0>;
+- compatible = "st,stm32-sai-sub-b";
+- reg = <0x24 0x20>;
+- clocks = <&rcc SAI2_K>;
+- clock-names = "sai_ck";
+- dmas = <&dmamux1 90 0x400 0x01>;
++ cec: cec@40016000 {
++ compatible = "st,stm32-cec";
++ reg = <0x40016000 0x400>;
++ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc CEC_K>, <&rcc CEC>;
++ clock-names = "cec", "hdmi-cec";
+ status = "disabled";
+ };
+- };
+
+- sai3: sai@4400c000 {
+- compatible = "st,stm32h7-sai";
+- #address-cells = <1>;
+- #size-cells = <1>;
+- ranges = <0 0x4400c000 0x400>;
+- reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
+- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+- resets = <&rcc SAI3_R>;
+- status = "disabled";
++ dac: dac@40017000 {
++ compatible = "st,stm32h7-dac-core";
++ reg = <0x40017000 0x400>;
++ clocks = <&rcc DAC12>;
++ clock-names = "pclk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
+
+- sai3a: audio-controller@4400c004 {
+- #sound-dai-cells = <0>;
+- compatible = "st,stm32-sai-sub-a";
+- reg = <0x04 0x20>;
+- clocks = <&rcc SAI3_K>;
+- clock-names = "sai_ck";
+- dmas = <&dmamux1 113 0x400 0x01>;
++ dac1: dac@1 {
++ compatible = "st,stm32-dac";
++ #io-channel-cells = <1>;
++ reg = <1>;
++ status = "disabled";
++ };
++
++ dac2: dac@2 {
++ compatible = "st,stm32-dac";
++ #io-channel-cells = <1>;
++ reg = <2>;
++ status = "disabled";
++ };
++ };
++
++ uart7: serial@40018000 {
++ compatible = "st,stm32h7-uart";
++ reg = <0x40018000 0x400>;
++ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc UART7_K>;
++ wakeup-source;
++ dmas = <&dmamux1 79 0x400 0x15>,
++ <&dmamux1 80 0x400 0x11>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+- sai3b: audio-controller@4400c024 {
+- #sound-dai-cells = <0>;
+- compatible = "st,stm32-sai-sub-b";
+- reg = <0x24 0x20>;
+- clocks = <&rcc SAI3_K>;
+- clock-names = "sai_ck";
+- dmas = <&dmamux1 114 0x400 0x01>;
++ uart8: serial@40019000 {
++ compatible = "st,stm32h7-uart";
++ reg = <0x40019000 0x400>;
++ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc UART8_K>;
++ wakeup-source;
++ dmas = <&dmamux1 81 0x400 0x15>,
++ <&dmamux1 82 0x400 0x11>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+- };
+
+- dfsdm: dfsdm@4400d000 {
+- compatible = "st,stm32mp1-dfsdm";
+- reg = <0x4400d000 0x800>;
+- clocks = <&rcc DFSDM_K>;
+- clock-names = "dfsdm";
+- #address-cells = <1>;
+- #size-cells = <0>;
+- status = "disabled";
++ timers1: timer@44000000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x44000000 0x400>;
++ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "brk", "up", "trg-com", "cc";
++ clocks = <&rcc TIM1_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 11 0x400 0x1>,
++ <&dmamux1 12 0x400 0x1>,
++ <&dmamux1 13 0x400 0x1>,
++ <&dmamux1 14 0x400 0x1>,
++ <&dmamux1 15 0x400 0x1>,
++ <&dmamux1 16 0x400 0x1>,
++ <&dmamux1 17 0x400 0x1>;
++ dma-names = "ch1", "ch2", "ch3", "ch4",
++ "up", "trig", "com";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
+
+- dfsdm0: filter@0 {
+- compatible = "st,stm32-dfsdm-adc";
+- #io-channel-cells = <1>;
+- reg = <0>;
+- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmamux1 101 0x400 0x01>;
+- dma-names = "rx";
+- status = "disabled";
++ timer@0 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <0>;
++ status = "disabled";
++ };
++
++ counter {
++ compatible = "st,stm32-timer-counter";
++ status = "disabled";
++ };
+ };
+
+- dfsdm1: filter@1 {
+- compatible = "st,stm32-dfsdm-adc";
+- #io-channel-cells = <1>;
+- reg = <1>;
+- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmamux1 102 0x400 0x01>;
+- dma-names = "rx";
+- status = "disabled";
++ timers8: timer@44001000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x44001000 0x400>;
++ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "brk", "up", "trg-com", "cc";
++ clocks = <&rcc TIM8_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 47 0x400 0x1>,
++ <&dmamux1 48 0x400 0x1>,
++ <&dmamux1 49 0x400 0x1>,
++ <&dmamux1 50 0x400 0x1>,
++ <&dmamux1 51 0x400 0x1>,
++ <&dmamux1 52 0x400 0x1>,
++ <&dmamux1 53 0x400 0x1>;
++ dma-names = "ch1", "ch2", "ch3", "ch4",
++ "up", "trig", "com";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ timer@7 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <7>;
++ status = "disabled";
++ };
++
++ counter {
++ compatible = "st,stm32-timer-counter";
++ status = "disabled";
++ };
+ };
+
+- dfsdm2: filter@2 {
+- compatible = "st,stm32-dfsdm-adc";
+- #io-channel-cells = <1>;
+- reg = <2>;
+- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmamux1 103 0x400 0x01>;
+- dma-names = "rx";
++ usart6: serial@44003000 {
++ compatible = "st,stm32h7-uart";
++ reg = <0x44003000 0x400>;
++ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc USART6_K>;
++ wakeup-source;
++ dmas = <&dmamux1 71 0x400 0x15>,
++ <&dmamux1 72 0x400 0x11>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+- dfsdm3: filter@3 {
+- compatible = "st,stm32-dfsdm-adc";
+- #io-channel-cells = <1>;
+- reg = <3>;
+- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmamux1 104 0x400 0x01>;
+- dma-names = "rx";
++ i2s1: audio-controller@44004000 {
++ compatible = "st,stm32h7-i2s";
++ #sound-dai-cells = <0>;
++ reg = <0x44004000 0x400>;
++ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmamux1 37 0x400 0x01>,
++ <&dmamux1 38 0x400 0x01>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+- dfsdm4: filter@4 {
+- compatible = "st,stm32-dfsdm-adc";
+- #io-channel-cells = <1>;
+- reg = <4>;
+- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmamux1 91 0x400 0x01>;
+- dma-names = "rx";
++ spi1: spi@44004000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32h7-spi";
++ reg = <0x44004000 0x400>;
++ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SPI1_K>;
++ resets = <&rcc SPI1_R>;
++ dmas = <&dmamux1 37 0x400 0x05>,
++ <&dmamux1 38 0x400 0x05>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+- dfsdm5: filter@5 {
+- compatible = "st,stm32-dfsdm-adc";
+- #io-channel-cells = <1>;
+- reg = <5>;
+- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmamux1 92 0x400 0x01>;
+- dma-names = "rx";
++ spi4: spi@44005000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32h7-spi";
++ reg = <0x44005000 0x400>;
++ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SPI4_K>;
++ resets = <&rcc SPI4_R>;
++ dmas = <&dmamux1 83 0x400 0x05>,
++ <&dmamux1 84 0x400 0x05>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+- };
+
+- dma1: dma-controller@48000000 {
+- compatible = "st,stm32-dma";
+- reg = <0x48000000 0x400>;
+- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc DMA1>;
+- resets = <&rcc DMA1_R>;
+- #dma-cells = <4>;
+- st,mem2mem;
+- dma-requests = <8>;
+- };
++ timers15: timer@44006000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x44006000 0x400>;
++ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM15_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 105 0x400 0x1>,
++ <&dmamux1 106 0x400 0x1>,
++ <&dmamux1 107 0x400 0x1>,
++ <&dmamux1 108 0x400 0x1>;
++ dma-names = "ch1", "up", "trig", "com";
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
+
+- dma2: dma-controller@48001000 {
+- compatible = "st,stm32-dma";
+- reg = <0x48001000 0x400>;
+- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc DMA2>;
+- resets = <&rcc DMA2_R>;
+- #dma-cells = <4>;
+- st,mem2mem;
+- dma-requests = <8>;
+- };
++ timer@14 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <14>;
++ status = "disabled";
++ };
++ };
+
+- dmamux1: dma-router@48002000 {
+- compatible = "st,stm32h7-dmamux";
+- reg = <0x48002000 0x40>;
+- #dma-cells = <3>;
+- dma-requests = <128>;
+- dma-masters = <&dma1 &dma2>;
+- dma-channels = <16>;
+- clocks = <&rcc DMAMUX>;
+- resets = <&rcc DMAMUX_R>;
+- };
++ timers16: timer@44007000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-timers";
++ reg = <0x44007000 0x400>;
++ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM16_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 109 0x400 0x1>,
++ <&dmamux1 110 0x400 0x1>;
++ dma-names = "ch1", "up";
++ status = "disabled";
+
+- adc: adc@48003000 {
+- compatible = "st,stm32mp1-adc-core";
+- reg = <0x48003000 0x400>;
+- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+- clock-names = "bus", "adc";
+- interrupt-controller;
+- st,syscfg = <&syscfg>;
+- #interrupt-cells = <1>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- status = "disabled";
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++ timer@15 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <15>;
++ status = "disabled";
++ };
++ };
+
+- adc1: adc@0 {
+- compatible = "st,stm32mp1-adc";
+- #io-channel-cells = <1>;
++ timers17: timer@44008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+- reg = <0x0>;
+- interrupt-parent = <&adc>;
+- interrupts = <0>;
+- dmas = <&dmamux1 9 0x400 0x01>;
+- dma-names = "rx";
++ compatible = "st,stm32-timers";
++ reg = <0x44008000 0x400>;
++ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "global";
++ clocks = <&rcc TIM17_K>;
++ clock-names = "int";
++ dmas = <&dmamux1 111 0x400 0x1>,
++ <&dmamux1 112 0x400 0x1>;
++ dma-names = "ch1", "up";
+ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ timer@16 {
++ compatible = "st,stm32h7-timer-trigger";
++ reg = <16>;
++ status = "disabled";
++ };
+ };
+
+- adc2: adc@100 {
+- compatible = "st,stm32mp1-adc";
+- #io-channel-cells = <1>;
++ spi5: spi@44009000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+- reg = <0x100>;
+- interrupt-parent = <&adc>;
+- interrupts = <1>;
+- dmas = <&dmamux1 10 0x400 0x01>;
+- dma-names = "rx";
+- nvmem-cells = <&vrefint>;
+- nvmem-cell-names = "vrefint";
++ compatible = "st,stm32h7-spi";
++ reg = <0x44009000 0x400>;
++ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SPI5_K>;
++ resets = <&rcc SPI5_R>;
++ dmas = <&dmamux1 85 0x400 0x05>,
++ <&dmamux1 86 0x400 0x05>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+- channel@13 {
+- reg = <13>;
+- label = "vrefint";
++ };
++
++ sai1: sai@4400a000 {
++ compatible = "st,stm32h7-sai";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0x4400a000 0x400>;
++ reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
++ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&rcc SAI1_R>;
++ status = "disabled";
++
++ sai1a: audio-controller@4400a004 {
++ #sound-dai-cells = <0>;
++
++ compatible = "st,stm32-sai-sub-a";
++ reg = <0x4 0x20>;
++ clocks = <&rcc SAI1_K>;
++ clock-names = "sai_ck";
++ dmas = <&dmamux1 87 0x400 0x01>;
++ status = "disabled";
+ };
+- channel@14 {
+- reg = <14>;
+- label = "vddcore";
++
++ sai1b: audio-controller@4400a024 {
++ #sound-dai-cells = <0>;
++ compatible = "st,stm32-sai-sub-b";
++ reg = <0x24 0x20>;
++ clocks = <&rcc SAI1_K>;
++ clock-names = "sai_ck";
++ dmas = <&dmamux1 88 0x400 0x01>;
++ status = "disabled";
+ };
+ };
+- };
+
+- sdmmc3: mmc@48004000 {
+- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+- arm,primecell-periphid = <0x00253180>;
+- reg = <0x48004000 0x400>;
+- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SDMMC3_K>;
+- clock-names = "apb_pclk";
+- resets = <&rcc SDMMC3_R>;
+- cap-sd-highspeed;
+- cap-mmc-highspeed;
+- max-frequency = <120000000>;
+- status = "disabled";
+- };
+-
+- usbotg_hs: usb-otg@49000000 {
+- compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+- reg = <0x49000000 0x10000>;
+- clocks = <&rcc USBO_K>, <&usbphyc>;
+- clock-names = "otg", "utmi";
+- resets = <&rcc USBO_R>;
+- reset-names = "dwc2";
+- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+- g-rx-fifo-size = <512>;
+- g-np-tx-fifo-size = <32>;
+- g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+- dr_mode = "otg";
+- otg-rev = <0x200>;
+- usb33d-supply = <&usb33>;
+- status = "disabled";
+- };
++ sai2: sai@4400b000 {
++ compatible = "st,stm32h7-sai";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0x4400b000 0x400>;
++ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
++ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&rcc SAI2_R>;
++ status = "disabled";
+
+- ipcc: mailbox@4c001000 {
+- compatible = "st,stm32mp1-ipcc";
+- #mbox-cells = <1>;
+- reg = <0x4c001000 0x400>;
+- st,proc-id = <0>;
+- interrupts-extended =
+- <&exti 61 IRQ_TYPE_LEVEL_HIGH>,
+- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "rx", "tx";
+- clocks = <&rcc IPCC>;
+- wakeup-source;
+- status = "disabled";
+- };
++ sai2a: audio-controller@4400b004 {
++ #sound-dai-cells = <0>;
++ compatible = "st,stm32-sai-sub-a";
++ reg = <0x4 0x20>;
++ clocks = <&rcc SAI2_K>;
++ clock-names = "sai_ck";
++ dmas = <&dmamux1 89 0x400 0x01>;
++ status = "disabled";
++ };
+
+- dcmi: dcmi@4c006000 {
+- compatible = "st,stm32-dcmi";
+- reg = <0x4c006000 0x400>;
+- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+- resets = <&rcc CAMITF_R>;
+- clocks = <&rcc DCMI>;
+- clock-names = "mclk";
+- dmas = <&dmamux1 75 0x400 0x01>;
+- dma-names = "tx";
+- status = "disabled";
+- };
++ sai2b: audio-controller@4400b024 {
++ #sound-dai-cells = <0>;
++ compatible = "st,stm32-sai-sub-b";
++ reg = <0x24 0x20>;
++ clocks = <&rcc SAI2_K>;
++ clock-names = "sai_ck";
++ dmas = <&dmamux1 90 0x400 0x01>;
++ status = "disabled";
++ };
++ };
+
+- rcc: rcc@50000000 {
+- compatible = "st,stm32mp1-rcc", "syscon";
+- reg = <0x50000000 0x1000>;
+- #clock-cells = <1>;
+- #reset-cells = <1>;
+- };
++ sai3: sai@4400c000 {
++ compatible = "st,stm32h7-sai";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0x4400c000 0x400>;
++ reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
++ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&rcc SAI3_R>;
++ status = "disabled";
+
+- pwr_regulators: pwr@50001000 {
+- compatible = "st,stm32mp1,pwr-reg";
+- reg = <0x50001000 0x10>;
++ sai3a: audio-controller@4400c004 {
++ #sound-dai-cells = <0>;
++ compatible = "st,stm32-sai-sub-a";
++ reg = <0x04 0x20>;
++ clocks = <&rcc SAI3_K>;
++ clock-names = "sai_ck";
++ dmas = <&dmamux1 113 0x400 0x01>;
++ status = "disabled";
++ };
+
+- reg11: reg11 {
+- regulator-name = "reg11";
+- regulator-min-microvolt = <1100000>;
+- regulator-max-microvolt = <1100000>;
++ sai3b: audio-controller@4400c024 {
++ #sound-dai-cells = <0>;
++ compatible = "st,stm32-sai-sub-b";
++ reg = <0x24 0x20>;
++ clocks = <&rcc SAI3_K>;
++ clock-names = "sai_ck";
++ dmas = <&dmamux1 114 0x400 0x01>;
++ status = "disabled";
++ };
+ };
+
+- reg18: reg18 {
+- regulator-name = "reg18";
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- };
++ dfsdm: dfsdm@4400d000 {
++ compatible = "st,stm32mp1-dfsdm";
++ reg = <0x4400d000 0x800>;
++ clocks = <&rcc DFSDM_K>;
++ clock-names = "dfsdm";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
+
+- usb33: usb33 {
+- regulator-name = "usb33";
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- };
+- };
++ dfsdm0: filter@0 {
++ compatible = "st,stm32-dfsdm-adc";
++ #io-channel-cells = <1>;
++ reg = <0>;
++ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmamux1 101 0x400 0x01>;
++ dma-names = "rx";
++ status = "disabled";
++ };
+
+- pwr_mcu: pwr_mcu@50001014 {
+- compatible = "st,stm32mp151-pwr-mcu", "syscon";
+- reg = <0x50001014 0x4>;
+- };
++ dfsdm1: filter@1 {
++ compatible = "st,stm32-dfsdm-adc";
++ #io-channel-cells = <1>;
++ reg = <1>;
++ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmamux1 102 0x400 0x01>;
++ dma-names = "rx";
++ status = "disabled";
++ };
+
+- exti: interrupt-controller@5000d000 {
+- compatible = "st,stm32mp1-exti", "syscon";
+- interrupt-controller;
+- #interrupt-cells = <2>;
+- reg = <0x5000d000 0x400>;
+- };
++ dfsdm2: filter@2 {
++ compatible = "st,stm32-dfsdm-adc";
++ #io-channel-cells = <1>;
++ reg = <2>;
++ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmamux1 103 0x400 0x01>;
++ dma-names = "rx";
++ status = "disabled";
++ };
+
+- syscfg: syscon@50020000 {
+- compatible = "st,stm32mp157-syscfg", "syscon";
+- reg = <0x50020000 0x400>;
+- clocks = <&rcc SYSCFG>;
+- };
++ dfsdm3: filter@3 {
++ compatible = "st,stm32-dfsdm-adc";
++ #io-channel-cells = <1>;
++ reg = <3>;
++ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmamux1 104 0x400 0x01>;
++ dma-names = "rx";
++ status = "disabled";
++ };
+
+- lptimer2: timer@50021000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-lptimer";
+- reg = <0x50021000 0x400>;
+- interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc LPTIM2_K>;
+- clock-names = "mux";
+- wakeup-source;
+- status = "disabled";
++ dfsdm4: filter@4 {
++ compatible = "st,stm32-dfsdm-adc";
++ #io-channel-cells = <1>;
++ reg = <4>;
++ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmamux1 91 0x400 0x01>;
++ dma-names = "rx";
++ status = "disabled";
++ };
+
+- pwm {
+- compatible = "st,stm32-pwm-lp";
+- #pwm-cells = <3>;
+- status = "disabled";
++ dfsdm5: filter@5 {
++ compatible = "st,stm32-dfsdm-adc";
++ #io-channel-cells = <1>;
++ reg = <5>;
++ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmamux1 92 0x400 0x01>;
++ dma-names = "rx";
++ status = "disabled";
++ };
+ };
+
+- trigger@1 {
+- compatible = "st,stm32-lptimer-trigger";
+- reg = <1>;
++ dma1: dma-controller@48000000 {
++ compatible = "st,stm32-dma";
++ reg = <0x48000000 0x400>;
++ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc DMA1>;
++ resets = <&rcc DMA1_R>;
++ #dma-cells = <4>;
++ st,mem2mem;
++ dma-requests = <8>;
++ };
++
++ dma2: dma-controller@48001000 {
++ compatible = "st,stm32-dma";
++ reg = <0x48001000 0x400>;
++ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc DMA2>;
++ resets = <&rcc DMA2_R>;
++ #dma-cells = <4>;
++ st,mem2mem;
++ dma-requests = <8>;
++ };
++
++ dmamux1: dma-router@48002000 {
++ compatible = "st,stm32h7-dmamux";
++ reg = <0x48002000 0x40>;
++ #dma-cells = <3>;
++ dma-requests = <128>;
++ dma-masters = <&dma1 &dma2>;
++ dma-channels = <16>;
++ clocks = <&rcc DMAMUX>;
++ resets = <&rcc DMAMUX_R>;
++ };
++
++ adc: adc@48003000 {
++ compatible = "st,stm32mp1-adc-core";
++ reg = <0x48003000 0x400>;
++ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc ADC12>, <&rcc ADC12_K>;
++ clock-names = "bus", "adc";
++ interrupt-controller;
++ st,syscfg = <&syscfg>;
++ #interrupt-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
+ status = "disabled";
+- };
+
+- counter {
+- compatible = "st,stm32-lptimer-counter";
+- status = "disabled";
+- };
+- };
++ adc1: adc@0 {
++ compatible = "st,stm32mp1-adc";
++ #io-channel-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>;
++ interrupt-parent = <&adc>;
++ interrupts = <0>;
++ dmas = <&dmamux1 9 0x400 0x01>;
++ dma-names = "rx";
++ status = "disabled";
++ };
+
+- lptimer3: timer@50022000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32-lptimer";
+- reg = <0x50022000 0x400>;
+- interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc LPTIM3_K>;
+- clock-names = "mux";
+- wakeup-source;
+- status = "disabled";
++ adc2: adc@100 {
++ compatible = "st,stm32mp1-adc";
++ #io-channel-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x100>;
++ interrupt-parent = <&adc>;
++ interrupts = <1>;
++ dmas = <&dmamux1 10 0x400 0x01>;
++ dma-names = "rx";
++ nvmem-cells = <&vrefint>;
++ nvmem-cell-names = "vrefint";
++ status = "disabled";
++ channel@13 {
++ reg = <13>;
++ label = "vrefint";
++ };
++ channel@14 {
++ reg = <14>;
++ label = "vddcore";
++ };
++ };
++ };
+
+- pwm {
+- compatible = "st,stm32-pwm-lp";
+- #pwm-cells = <3>;
++ sdmmc3: mmc@48004000 {
++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
++ arm,primecell-periphid = <0x00253180>;
++ reg = <0x48004000 0x400>;
++ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SDMMC3_K>;
++ clock-names = "apb_pclk";
++ resets = <&rcc SDMMC3_R>;
++ cap-sd-highspeed;
++ cap-mmc-highspeed;
++ max-frequency = <120000000>;
+ status = "disabled";
+ };
+
+- trigger@2 {
+- compatible = "st,stm32-lptimer-trigger";
+- reg = <2>;
++ usbotg_hs: usb-otg@49000000 {
++ compatible = "st,stm32mp15-hsotg", "snps,dwc2";
++ reg = <0x49000000 0x10000>;
++ clocks = <&rcc USBO_K>, <&usbphyc>;
++ clock-names = "otg", "utmi";
++ resets = <&rcc USBO_R>;
++ reset-names = "dwc2";
++ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
++ g-rx-fifo-size = <512>;
++ g-np-tx-fifo-size = <32>;
++ g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
++ dr_mode = "otg";
++ otg-rev = <0x200>;
++ usb33d-supply = <&usb33>;
+ status = "disabled";
+ };
+- };
+
+- lptimer4: timer@50023000 {
+- compatible = "st,stm32-lptimer";
+- reg = <0x50023000 0x400>;
+- interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc LPTIM4_K>;
+- clock-names = "mux";
+- wakeup-source;
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm-lp";
+- #pwm-cells = <3>;
++ dcmi: dcmi@4c006000 {
++ compatible = "st,stm32-dcmi";
++ reg = <0x4c006000 0x400>;
++ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&rcc CAMITF_R>;
++ clocks = <&rcc DCMI>;
++ clock-names = "mclk";
++ dmas = <&dmamux1 75 0x400 0x01>;
++ dma-names = "tx";
+ status = "disabled";
+ };
+- };
+
+- lptimer5: timer@50024000 {
+- compatible = "st,stm32-lptimer";
+- reg = <0x50024000 0x400>;
+- interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc LPTIM5_K>;
+- clock-names = "mux";
+- wakeup-source;
+- status = "disabled";
+-
+- pwm {
+- compatible = "st,stm32-pwm-lp";
+- #pwm-cells = <3>;
++ lptimer2: timer@50021000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-lptimer";
++ reg = <0x50021000 0x400>;
++ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc LPTIM2_K>;
++ clock-names = "mux";
++ wakeup-source;
+ status = "disabled";
+- };
+- };
+
+- vrefbuf: vrefbuf@50025000 {
+- compatible = "st,stm32-vrefbuf";
+- reg = <0x50025000 0x8>;
+- regulator-min-microvolt = <1500000>;
+- regulator-max-microvolt = <2500000>;
+- clocks = <&rcc VREF>;
+- status = "disabled";
+- };
++ pwm {
++ compatible = "st,stm32-pwm-lp";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
+
+- sai4: sai@50027000 {
+- compatible = "st,stm32h7-sai";
+- #address-cells = <1>;
+- #size-cells = <1>;
+- ranges = <0 0x50027000 0x400>;
+- reg = <0x50027000 0x4>, <0x500273f0 0x10>;
+- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+- resets = <&rcc SAI4_R>;
+- status = "disabled";
++ trigger@1 {
++ compatible = "st,stm32-lptimer-trigger";
++ reg = <1>;
++ status = "disabled";
++ };
+
+- sai4a: audio-controller@50027004 {
+- #sound-dai-cells = <0>;
+- compatible = "st,stm32-sai-sub-a";
+- reg = <0x04 0x20>;
+- clocks = <&rcc SAI4_K>;
+- clock-names = "sai_ck";
+- dmas = <&dmamux1 99 0x400 0x01>;
+- status = "disabled";
++ counter {
++ compatible = "st,stm32-lptimer-counter";
++ status = "disabled";
++ };
+ };
+
+- sai4b: audio-controller@50027024 {
+- #sound-dai-cells = <0>;
+- compatible = "st,stm32-sai-sub-b";
+- reg = <0x24 0x20>;
+- clocks = <&rcc SAI4_K>;
+- clock-names = "sai_ck";
+- dmas = <&dmamux1 100 0x400 0x01>;
++ lptimer3: timer@50022000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32-lptimer";
++ reg = <0x50022000 0x400>;
++ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc LPTIM3_K>;
++ clock-names = "mux";
++ wakeup-source;
+ status = "disabled";
+- };
+- };
+-
+- dts: thermal@50028000 {
+- compatible = "st,stm32-thermal";
+- reg = <0x50028000 0x100>;
+- interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc TMPSENS>;
+- clock-names = "pclk";
+- #thermal-sensor-cells = <0>;
+- status = "disabled";
+- };
+-
+- hash1: hash@54002000 {
+- compatible = "st,stm32f756-hash";
+- reg = <0x54002000 0x400>;
+- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc HASH1>;
+- resets = <&rcc HASH1_R>;
+- dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
+- dma-names = "in";
+- dma-maxburst = <2>;
+- status = "disabled";
+- };
+-
+- rng1: rng@54003000 {
+- compatible = "st,stm32-rng";
+- reg = <0x54003000 0x400>;
+- clocks = <&rcc RNG1_K>;
+- resets = <&rcc RNG1_R>;
+- status = "disabled";
+- };
+-
+- mdma1: dma-controller@58000000 {
+- compatible = "st,stm32h7-mdma";
+- reg = <0x58000000 0x1000>;
+- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc MDMA>;
+- resets = <&rcc MDMA_R>;
+- #dma-cells = <5>;
+- dma-channels = <32>;
+- dma-requests = <48>;
+- };
+
+- fmc: memory-controller@58002000 {
+- #address-cells = <2>;
+- #size-cells = <1>;
+- compatible = "st,stm32mp1-fmc2-ebi";
+- reg = <0x58002000 0x1000>;
+- clocks = <&rcc FMC_K>;
+- resets = <&rcc FMC_R>;
+- status = "disabled";
++ pwm {
++ compatible = "st,stm32-pwm-lp";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
+
+- ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+- <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+- <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+- <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+- <4 0 0x80000000 0x10000000>; /* NAND */
+-
+- nand-controller@4,0 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32mp1-fmc2-nfc";
+- reg = <4 0x00000000 0x1000>,
+- <4 0x08010000 0x1000>,
+- <4 0x08020000 0x1000>,
+- <4 0x01000000 0x1000>,
+- <4 0x09010000 0x1000>,
+- <4 0x09020000 0x1000>;
+- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
+- <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
+- <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+- dma-names = "tx", "rx", "ecc";
+- status = "disabled";
++ trigger@2 {
++ compatible = "st,stm32-lptimer-trigger";
++ reg = <2>;
++ status = "disabled";
++ };
+ };
+- };
+-
+- qspi: spi@58003000 {
+- compatible = "st,stm32f469-qspi";
+- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+- reg-names = "qspi", "qspi_mm";
+- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
+- <&mdma1 22 0x2 0x10100008 0x0 0x0>;
+- dma-names = "tx", "rx";
+- clocks = <&rcc QSPI_K>;
+- resets = <&rcc QSPI_R>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- status = "disabled";
+- };
+
+- sdmmc1: mmc@58005000 {
+- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+- arm,primecell-periphid = <0x00253180>;
+- reg = <0x58005000 0x1000>;
+- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SDMMC1_K>;
+- clock-names = "apb_pclk";
+- resets = <&rcc SDMMC1_R>;
+- cap-sd-highspeed;
+- cap-mmc-highspeed;
+- max-frequency = <120000000>;
+- status = "disabled";
+- };
+-
+- sdmmc2: mmc@58007000 {
+- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+- arm,primecell-periphid = <0x00253180>;
+- reg = <0x58007000 0x1000>;
+- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SDMMC2_K>;
+- clock-names = "apb_pclk";
+- resets = <&rcc SDMMC2_R>;
+- cap-sd-highspeed;
+- cap-mmc-highspeed;
+- max-frequency = <120000000>;
+- status = "disabled";
+- };
+-
+- crc1: crc@58009000 {
+- compatible = "st,stm32f7-crc";
+- reg = <0x58009000 0x400>;
+- clocks = <&rcc CRC1>;
+- status = "disabled";
+- };
+-
+- ethernet0: ethernet@5800a000 {
+- compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
+- reg = <0x5800a000 0x2000>;
+- reg-names = "stmmaceth";
+- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "macirq";
+- clock-names = "stmmaceth",
+- "mac-clk-tx",
+- "mac-clk-rx",
+- "eth-ck",
+- "ptp_ref",
+- "ethstp";
+- clocks = <&rcc ETHMAC>,
+- <&rcc ETHTX>,
+- <&rcc ETHRX>,
+- <&rcc ETHCK_K>,
+- <&rcc ETHPTP_K>,
+- <&rcc ETHSTP>;
+- st,syscon = <&syscfg 0x4>;
+- snps,mixed-burst;
+- snps,pbl = <2>;
+- snps,en-tx-lpi-clockgating;
+- snps,axi-config = <&stmmac_axi_config_0>;
+- snps,tso;
+- status = "disabled";
++ lptimer4: timer@50023000 {
++ compatible = "st,stm32-lptimer";
++ reg = <0x50023000 0x400>;
++ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc LPTIM4_K>;
++ clock-names = "mux";
++ wakeup-source;
++ status = "disabled";
+
+- stmmac_axi_config_0: stmmac-axi-config {
+- snps,wr_osr_lmt = <0x7>;
+- snps,rd_osr_lmt = <0x7>;
+- snps,blen = <0 0 0 0 16 8 4>;
++ pwm {
++ compatible = "st,stm32-pwm-lp";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
+ };
+- };
+
+- usbh_ohci: usb@5800c000 {
+- compatible = "generic-ohci";
+- reg = <0x5800c000 0x1000>;
+- clocks = <&usbphyc>, <&rcc USBH>;
+- resets = <&rcc USBH_R>;
+- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+- status = "disabled";
+- };
++ lptimer5: timer@50024000 {
++ compatible = "st,stm32-lptimer";
++ reg = <0x50024000 0x400>;
++ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc LPTIM5_K>;
++ clock-names = "mux";
++ wakeup-source;
++ status = "disabled";
+
+- usbh_ehci: usb@5800d000 {
+- compatible = "generic-ehci";
+- reg = <0x5800d000 0x1000>;
+- clocks = <&usbphyc>, <&rcc USBH>;
+- resets = <&rcc USBH_R>;
+- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+- companion = <&usbh_ohci>;
+- status = "disabled";
+- };
++ pwm {
++ compatible = "st,stm32-pwm-lp";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++ };
+
+- ltdc: display-controller@5a001000 {
+- compatible = "st,stm32-ltdc";
+- reg = <0x5a001000 0x400>;
+- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc LTDC_PX>;
+- clock-names = "lcd";
+- resets = <&rcc LTDC_R>;
+- status = "disabled";
+- };
++ vrefbuf: vrefbuf@50025000 {
++ compatible = "st,stm32-vrefbuf";
++ reg = <0x50025000 0x8>;
++ regulator-min-microvolt = <1500000>;
++ regulator-max-microvolt = <2500000>;
++ clocks = <&rcc VREF>;
++ status = "disabled";
++ };
+
+- iwdg2: watchdog@5a002000 {
+- compatible = "st,stm32mp1-iwdg";
+- reg = <0x5a002000 0x400>;
+- clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
+- clock-names = "pclk", "lsi";
+- status = "disabled";
+- };
++ sai4: sai@50027000 {
++ compatible = "st,stm32h7-sai";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0x50027000 0x400>;
++ reg = <0x50027000 0x4>, <0x500273f0 0x10>;
++ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&rcc SAI4_R>;
++ status = "disabled";
+
+- usbphyc: usbphyc@5a006000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- #clock-cells = <0>;
+- compatible = "st,stm32mp1-usbphyc";
+- reg = <0x5a006000 0x1000>;
+- clocks = <&rcc USBPHY_K>;
+- resets = <&rcc USBPHY_R>;
+- vdda1v1-supply = <®11>;
+- vdda1v8-supply = <®18>;
+- status = "disabled";
++ sai4a: audio-controller@50027004 {
++ #sound-dai-cells = <0>;
++ compatible = "st,stm32-sai-sub-a";
++ reg = <0x04 0x20>;
++ clocks = <&rcc SAI4_K>;
++ clock-names = "sai_ck";
++ dmas = <&dmamux1 99 0x400 0x01>;
++ status = "disabled";
++ };
+
+- usbphyc_port0: usb-phy@0 {
+- #phy-cells = <0>;
+- reg = <0>;
++ sai4b: audio-controller@50027024 {
++ #sound-dai-cells = <0>;
++ compatible = "st,stm32-sai-sub-b";
++ reg = <0x24 0x20>;
++ clocks = <&rcc SAI4_K>;
++ clock-names = "sai_ck";
++ dmas = <&dmamux1 100 0x400 0x01>;
++ status = "disabled";
++ };
+ };
+
+- usbphyc_port1: usb-phy@1 {
+- #phy-cells = <1>;
+- reg = <1>;
++ hash1: hash@54002000 {
++ compatible = "st,stm32f756-hash";
++ reg = <0x54002000 0x400>;
++ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc HASH1>;
++ resets = <&rcc HASH1_R>;
++ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
++ dma-names = "in";
++ dma-maxburst = <2>;
++ status = "disabled";
+ };
+- };
+-
+- usart1: serial@5c000000 {
+- compatible = "st,stm32h7-uart";
+- reg = <0x5c000000 0x400>;
+- interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc USART1_K>;
+- wakeup-source;
+- status = "disabled";
+- };
+
+- spi6: spi@5c001000 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+- compatible = "st,stm32h7-spi";
+- reg = <0x5c001000 0x400>;
+- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc SPI6_K>;
+- resets = <&rcc SPI6_R>;
+- dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
+- <&mdma1 35 0x0 0x40002 0x0 0x0>;
+- dma-names = "rx", "tx";
+- status = "disabled";
+- };
++ rng1: rng@54003000 {
++ compatible = "st,stm32-rng";
++ reg = <0x54003000 0x400>;
++ clocks = <&rcc RNG1_K>;
++ resets = <&rcc RNG1_R>;
++ status = "disabled";
++ };
+
+- i2c4: i2c@5c002000 {
+- compatible = "st,stm32mp15-i2c";
+- reg = <0x5c002000 0x400>;
+- interrupt-names = "event", "error";
+- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc I2C4_K>;
+- resets = <&rcc I2C4_R>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- st,syscfg-fmp = <&syscfg 0x4 0x8>;
+- wakeup-source;
+- i2c-analog-filter;
+- status = "disabled";
+- };
++ fmc: memory-controller@58002000 {
++ #address-cells = <2>;
++ #size-cells = <1>;
++ compatible = "st,stm32mp1-fmc2-ebi";
++ reg = <0x58002000 0x1000>;
++ clocks = <&rcc FMC_K>;
++ resets = <&rcc FMC_R>;
++ status = "disabled";
++
++ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
++ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
++ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
++ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
++ <4 0 0x80000000 0x10000000>; /* NAND */
++
++ nand-controller@4,0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32mp1-fmc2-nfc";
++ reg = <4 0x00000000 0x1000>,
++ <4 0x08010000 0x1000>,
++ <4 0x08020000 0x1000>,
++ <4 0x01000000 0x1000>,
++ <4 0x09010000 0x1000>,
++ <4 0x09020000 0x1000>;
++ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
++ <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
++ <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
++ dma-names = "tx", "rx", "ecc";
++ status = "disabled";
++ };
++ };
+
+- rtc: rtc@5c004000 {
+- compatible = "st,stm32mp1-rtc";
+- reg = <0x5c004000 0x400>;
+- clocks = <&rcc RTCAPB>, <&rcc RTC>;
+- clock-names = "pclk", "rtc_ck";
+- interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
+- status = "disabled";
+- };
++ qspi: spi@58003000 {
++ compatible = "st,stm32f469-qspi";
++ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
++ reg-names = "qspi", "qspi_mm";
++ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
++ <&mdma1 22 0x2 0x10100008 0x0 0x0>;
++ dma-names = "tx", "rx";
++ clocks = <&rcc QSPI_K>;
++ resets = <&rcc QSPI_R>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
+
+- bsec: efuse@5c005000 {
+- compatible = "st,stm32mp15-bsec";
+- reg = <0x5c005000 0x400>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+- part_number_otp: part-number-otp@4 {
+- reg = <0x4 0x1>;
++ ethernet0: ethernet@5800a000 {
++ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
++ reg = <0x5800a000 0x2000>;
++ reg-names = "stmmaceth";
++ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq";
++ clock-names = "stmmaceth",
++ "mac-clk-tx",
++ "mac-clk-rx",
++ "eth-ck",
++ "ptp_ref",
++ "ethstp";
++ clocks = <&rcc ETHMAC>,
++ <&rcc ETHTX>,
++ <&rcc ETHRX>,
++ <&rcc ETHCK_K>,
++ <&rcc ETHPTP_K>,
++ <&rcc ETHSTP>;
++ st,syscon = <&syscfg 0x4>;
++ snps,mixed-burst;
++ snps,pbl = <2>;
++ snps,en-tx-lpi-clockgating;
++ snps,axi-config = <&stmmac_axi_config_0>;
++ snps,tso;
++ status = "disabled";
++
++ stmmac_axi_config_0: stmmac-axi-config {
++ snps,wr_osr_lmt = <0x7>;
++ snps,rd_osr_lmt = <0x7>;
++ snps,blen = <0 0 0 0 16 8 4>;
++ };
+ };
+- vrefint: vrefin-cal@52 {
+- reg = <0x52 0x2>;
++
++ usart1: serial@5c000000 {
++ compatible = "st,stm32h7-uart";
++ reg = <0x5c000000 0x400>;
++ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc USART1_K>;
++ wakeup-source;
++ status = "disabled";
+ };
+- ts_cal1: calib@5c {
+- reg = <0x5c 0x2>;
++
++ spi6: spi@5c001000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "st,stm32h7-spi";
++ reg = <0x5c001000 0x400>;
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc SPI6_K>;
++ resets = <&rcc SPI6_R>;
++ dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
++ <&mdma1 35 0x0 0x40002 0x0 0x0>;
++ dma-names = "rx", "tx";
++ status = "disabled";
+ };
+- ts_cal2: calib@5e {
+- reg = <0x5e 0x2>;
++
++ i2c4: i2c@5c002000 {
++ compatible = "st,stm32mp15-i2c";
++ reg = <0x5c002000 0x400>;
++ interrupt-names = "event", "error";
++ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc I2C4_K>;
++ resets = <&rcc I2C4_R>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ st,syscfg-fmp = <&syscfg 0x4 0x8>;
++ wakeup-source;
++ i2c-analog-filter;
++ status = "disabled";
+ };
+- };
+
+- i2c6: i2c@5c009000 {
+- compatible = "st,stm32mp15-i2c";
+- reg = <0x5c009000 0x400>;
+- interrupt-names = "event", "error";
+- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc I2C6_K>;
+- resets = <&rcc I2C6_R>;
+- #address-cells = <1>;
+- #size-cells = <0>;
+- st,syscfg-fmp = <&syscfg 0x4 0x20>;
+- wakeup-source;
+- i2c-analog-filter;
+- status = "disabled";
++ i2c6: i2c@5c009000 {
++ compatible = "st,stm32mp15-i2c";
++ reg = <0x5c009000 0x400>;
++ interrupt-names = "event", "error";
++ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc I2C6_K>;
++ resets = <&rcc I2C6_R>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ st,syscfg-fmp = <&syscfg 0x4 0x20>;
++ wakeup-source;
++ i2c-analog-filter;
++ status = "disabled";
++ };
+ };
+
+ tamp: tamp@5c00a000 {
+--- a/arch/arm/boot/dts/st/stm32mp153.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp153.dtsi
+@@ -28,32 +28,32 @@
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
++};
+
+- soc {
+- m_can1: can@4400e000 {
+- compatible = "bosch,m_can";
+- reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
+- reg-names = "m_can", "message_ram";
+- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+- clock-names = "hclk", "cclk";
+- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+- status = "disabled";
+- };
++&etzpc {
++ m_can1: can@4400e000 {
++ compatible = "bosch,m_can";
++ reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
++ reg-names = "m_can", "message_ram";
++ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
++ clock-names = "hclk", "cclk";
++ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
++ status = "disabled";
++ };
+
+- m_can2: can@4400f000 {
+- compatible = "bosch,m_can";
+- reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+- reg-names = "m_can", "message_ram";
+- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "int0", "int1";
+- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+- clock-names = "hclk", "cclk";
+- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+- status = "disabled";
+- };
++ m_can2: can@4400f000 {
++ compatible = "bosch,m_can";
++ reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
++ reg-names = "m_can", "message_ram";
++ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "int0", "int1";
++ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
++ clock-names = "hclk", "cclk";
++ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
++ status = "disabled";
+ };
+ };
+--- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi
+@@ -4,15 +4,13 @@
+ */
+
+-/ {
+- soc {
+- cryp1: cryp@54001000 {
+- compatible = "st,stm32mp1-cryp";
+- reg = <0x54001000 0x400>;
+- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+- clocks = <&rcc CRYP1>;
+- resets = <&rcc CRYP1_R>;
+- status = "disabled";
+- };
++&etzpc {
++ cryp1: cryp@54001000 {
++ compatible = "st,stm32mp1-cryp";
++ reg = <0x54001000 0x400>;
++ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&rcc CRYP1>;
++ resets = <&rcc CRYP1_R>;
++ status = "disabled";
+ };
+ };
--- /dev/null
+From 91ddf8509d0308e297f1876a024645cc3478e358 Mon Sep 17 00:00:00 2001
+Date: Fri, 5 Jan 2024 14:04:02 +0100
+Subject: [PATCH] ARM: dts: stm32: put ETZPC as an access controller for
+ STM32MP15x boards
+
+Reference ETZPC as an access-control-provider.
+
+For more information on which peripheral is securable or supports MCU
+isolation, please read the STM32MP15 reference manual
+
+---
+ arch/arm/boot/dts/st/stm32mp151.dtsi | 66 ++++++++++++++++++++++++++-
+ arch/arm/boot/dts/st/stm32mp153.dtsi | 2 +
+ arch/arm/boot/dts/st/stm32mp15xc.dtsi | 1 +
+ 3 files changed, 68 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/st/stm32mp151.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
+@@ -331,10 +331,11 @@
+ };
+
+ etzpc: bus@5c007000 {
+- compatible = "simple-bus";
++ compatible = "st,stm32-etzpc", "simple-bus";
+ reg = <0x5c007000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
++ #access-controller-cells = <1>;
+ ranges;
+
+ timers2: timer@40000000 {
+@@ -352,6 +353,7 @@
+ <&dmamux1 21 0x400 0x1>,
+ <&dmamux1 22 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up";
++ access-controllers = <&etzpc 16>;
+ status = "disabled";
+
+ pwm {
+@@ -388,6 +390,7 @@
+ <&dmamux1 27 0x400 0x1>,
+ <&dmamux1 28 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
++ access-controllers = <&etzpc 17>;
+ status = "disabled";
+
+ pwm {
+@@ -422,6 +425,7 @@
+ <&dmamux1 31 0x400 0x1>,
+ <&dmamux1 32 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4";
++ access-controllers = <&etzpc 18>;
+ status = "disabled";
+
+ pwm {
+@@ -458,6 +462,7 @@
+ <&dmamux1 59 0x400 0x1>,
+ <&dmamux1 60 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
++ access-controllers = <&etzpc 19>;
+ status = "disabled";
+
+ pwm {
+@@ -489,6 +494,7 @@
+ clock-names = "int";
+ dmas = <&dmamux1 69 0x400 0x1>;
+ dma-names = "up";
++ access-controllers = <&etzpc 20>;
+ status = "disabled";
+
+ timer@5 {
+@@ -509,6 +515,7 @@
+ clock-names = "int";
+ dmas = <&dmamux1 70 0x400 0x1>;
+ dma-names = "up";
++ access-controllers = <&etzpc 21>;
+ status = "disabled";
+
+ timer@6 {
+@@ -527,6 +534,7 @@
+ interrupt-names = "global";
+ clocks = <&rcc TIM12_K>;
+ clock-names = "int";
++ access-controllers = <&etzpc 22>;
+ status = "disabled";
+
+ pwm {
+@@ -551,6 +559,7 @@
+ interrupt-names = "global";
+ clocks = <&rcc TIM13_K>;
+ clock-names = "int";
++ access-controllers = <&etzpc 23>;
+ status = "disabled";
+
+ pwm {
+@@ -575,6 +584,7 @@
+ interrupt-names = "global";
+ clocks = <&rcc TIM14_K>;
+ clock-names = "int";
++ access-controllers = <&etzpc 24>;
+ status = "disabled";
+
+ pwm {
+@@ -599,6 +609,7 @@
+ clocks = <&rcc LPTIM1_K>;
+ clock-names = "mux";
+ wakeup-source;
++ access-controllers = <&etzpc 25>;
+ status = "disabled";
+
+ pwm {
+@@ -627,6 +638,7 @@
+ dmas = <&dmamux1 39 0x400 0x01>,
+ <&dmamux1 40 0x400 0x01>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 27>;
+ status = "disabled";
+ };
+
+@@ -641,6 +653,7 @@
+ dmas = <&dmamux1 39 0x400 0x05>,
+ <&dmamux1 40 0x400 0x05>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 27>;
+ status = "disabled";
+ };
+
+@@ -652,6 +665,7 @@
+ dmas = <&dmamux1 61 0x400 0x01>,
+ <&dmamux1 62 0x400 0x01>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 28>;
+ status = "disabled";
+ };
+
+@@ -666,6 +680,7 @@
+ dmas = <&dmamux1 61 0x400 0x05>,
+ <&dmamux1 62 0x400 0x05>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 28>;
+ status = "disabled";
+ };
+
+@@ -679,6 +694,7 @@
+ dmas = <&dmamux1 93 0x400 0x01>,
+ <&dmamux1 94 0x400 0x01>;
+ dma-names = "rx", "rx-ctrl";
++ access-controllers = <&etzpc 29>;
+ status = "disabled";
+ };
+
+@@ -691,6 +707,7 @@
+ dmas = <&dmamux1 43 0x400 0x15>,
+ <&dmamux1 44 0x400 0x11>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 30>;
+ status = "disabled";
+ };
+
+@@ -703,6 +720,7 @@
+ dmas = <&dmamux1 45 0x400 0x15>,
+ <&dmamux1 46 0x400 0x11>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 31>;
+ status = "disabled";
+ };
+
+@@ -715,6 +733,7 @@
+ dmas = <&dmamux1 63 0x400 0x15>,
+ <&dmamux1 64 0x400 0x11>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 32>;
+ status = "disabled";
+ };
+
+@@ -727,6 +746,7 @@
+ dmas = <&dmamux1 65 0x400 0x15>,
+ <&dmamux1 66 0x400 0x11>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 33>;
+ status = "disabled";
+ };
+
+@@ -743,6 +763,7 @@
+ st,syscfg-fmp = <&syscfg 0x4 0x1>;
+ wakeup-source;
+ i2c-analog-filter;
++ access-controllers = <&etzpc 34>;
+ status = "disabled";
+ };
+
+@@ -759,6 +780,7 @@
+ st,syscfg-fmp = <&syscfg 0x4 0x2>;
+ wakeup-source;
+ i2c-analog-filter;
++ access-controllers = <&etzpc 35>;
+ status = "disabled";
+ };
+
+@@ -775,6 +797,7 @@
+ st,syscfg-fmp = <&syscfg 0x4 0x4>;
+ wakeup-source;
+ i2c-analog-filter;
++ access-controllers = <&etzpc 36>;
+ status = "disabled";
+ };
+
+@@ -791,6 +814,7 @@
+ st,syscfg-fmp = <&syscfg 0x4 0x10>;
+ wakeup-source;
+ i2c-analog-filter;
++ access-controllers = <&etzpc 37>;
+ status = "disabled";
+ };
+
+@@ -800,6 +824,7 @@
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CEC_K>, <&rcc CEC>;
+ clock-names = "cec", "hdmi-cec";
++ access-controllers = <&etzpc 38>;
+ status = "disabled";
+ };
+
+@@ -810,6 +835,7 @@
+ clock-names = "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
++ access-controllers = <&etzpc 39>;
+ status = "disabled";
+
+ dac1: dac@1 {
+@@ -836,6 +862,7 @@
+ dmas = <&dmamux1 79 0x400 0x15>,
+ <&dmamux1 80 0x400 0x11>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 40>;
+ status = "disabled";
+ };
+
+@@ -848,6 +875,7 @@
+ dmas = <&dmamux1 81 0x400 0x15>,
+ <&dmamux1 82 0x400 0x11>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 41>;
+ status = "disabled";
+ };
+
+@@ -872,6 +900,7 @@
+ <&dmamux1 17 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4",
+ "up", "trig", "com";
++ access-controllers = <&etzpc 48>;
+ status = "disabled";
+
+ pwm {
+@@ -913,6 +942,7 @@
+ <&dmamux1 53 0x400 0x1>;
+ dma-names = "ch1", "ch2", "ch3", "ch4",
+ "up", "trig", "com";
++ access-controllers = <&etzpc 49>;
+ status = "disabled";
+
+ pwm {
+@@ -942,6 +972,7 @@
+ dmas = <&dmamux1 71 0x400 0x15>,
+ <&dmamux1 72 0x400 0x11>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 51>;
+ status = "disabled";
+ };
+
+@@ -953,6 +984,7 @@
+ dmas = <&dmamux1 37 0x400 0x01>,
+ <&dmamux1 38 0x400 0x01>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 52>;
+ status = "disabled";
+ };
+
+@@ -967,6 +999,7 @@
+ dmas = <&dmamux1 37 0x400 0x05>,
+ <&dmamux1 38 0x400 0x05>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 52>;
+ status = "disabled";
+ };
+
+@@ -981,6 +1014,7 @@
+ dmas = <&dmamux1 83 0x400 0x05>,
+ <&dmamux1 84 0x400 0x05>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 53>;
+ status = "disabled";
+ };
+
+@@ -998,6 +1032,7 @@
+ <&dmamux1 107 0x400 0x1>,
+ <&dmamux1 108 0x400 0x1>;
+ dma-names = "ch1", "up", "trig", "com";
++ access-controllers = <&etzpc 54>;
+ status = "disabled";
+
+ pwm {
+@@ -1025,6 +1060,7 @@
+ dmas = <&dmamux1 109 0x400 0x1>,
+ <&dmamux1 110 0x400 0x1>;
+ dma-names = "ch1", "up";
++ access-controllers = <&etzpc 55>;
+ status = "disabled";
+
+ pwm {
+@@ -1051,6 +1087,7 @@
+ dmas = <&dmamux1 111 0x400 0x1>,
+ <&dmamux1 112 0x400 0x1>;
+ dma-names = "ch1", "up";
++ access-controllers = <&etzpc 56>;
+ status = "disabled";
+
+ pwm {
+@@ -1077,6 +1114,7 @@
+ dmas = <&dmamux1 85 0x400 0x05>,
+ <&dmamux1 86 0x400 0x05>;
+ dma-names = "rx", "tx";
++ access-controllers = <&etzpc 57>;
+ status = "disabled";
+ };
+
+@@ -1088,6 +1126,7 @@
+ reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI1_R>;
++ access-controllers = <&etzpc 58>;
+ status = "disabled";
+
+ sai1a: audio-controller@4400a004 {
+@@ -1120,6 +1159,7 @@
+ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI2_R>;
++ access-controllers = <&etzpc 59>;
+ status = "disabled";
+
+ sai2a: audio-controller@4400b004 {
+@@ -1151,6 +1191,7 @@
+ reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI3_R>;
++ access-controllers = <&etzpc 60>;
+ status = "disabled";
+
+ sai3a: audio-controller@4400c004 {
+@@ -1181,6 +1222,7 @@
+ clock-names = "dfsdm";
+ #address-cells = <1>;
+ #size-cells = <0>;
++ access-controllers = <&etzpc 61>;
+ status = "disabled";
+
+ dfsdm0: filter@0 {
+@@ -1260,6 +1302,7 @@
+ #dma-cells = <4>;
+ st,mem2mem;
+ dma-requests = <8>;
++ access-controllers = <&etzpc 88>;
+ };
+
+ dma2: dma-controller@48001000 {
+@@ -1278,6 +1321,7 @@
+ #dma-cells = <4>;
+ st,mem2mem;
+ dma-requests = <8>;
++ access-controllers = <&etzpc 89>;
+ };
+
+ dmamux1: dma-router@48002000 {
+@@ -1289,6 +1333,7 @@
+ dma-channels = <16>;
+ clocks = <&rcc DMAMUX>;
+ resets = <&rcc DMAMUX_R>;
++ access-controllers = <&etzpc 90>;
+ };
+
+ adc: adc@48003000 {
+@@ -1303,6 +1348,7 @@
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
++ access-controllers = <&etzpc 72>;
+ status = "disabled";
+
+ adc1: adc@0 {
+@@ -1353,6 +1399,7 @@
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <120000000>;
++ access-controllers = <&etzpc 86>;
+ status = "disabled";
+ };
+
+@@ -1370,6 +1417,7 @@
+ dr_mode = "otg";
+ otg-rev = <0x200>;
+ usb33d-supply = <&usb33>;
++ access-controllers = <&etzpc 85>;
+ status = "disabled";
+ };
+
+@@ -1382,6 +1430,7 @@
+ clock-names = "mclk";
+ dmas = <&dmamux1 75 0x400 0x01>;
+ dma-names = "tx";
++ access-controllers = <&etzpc 70>;
+ status = "disabled";
+ };
+
+@@ -1394,6 +1443,7 @@
+ clocks = <&rcc LPTIM2_K>;
+ clock-names = "mux";
+ wakeup-source;
++ access-controllers = <&etzpc 64>;
+ status = "disabled";
+
+ pwm {
+@@ -1423,6 +1473,7 @@
+ clocks = <&rcc LPTIM3_K>;
+ clock-names = "mux";
+ wakeup-source;
++ access-controllers = <&etzpc 65>;
+ status = "disabled";
+
+ pwm {
+@@ -1445,6 +1496,7 @@
+ clocks = <&rcc LPTIM4_K>;
+ clock-names = "mux";
+ wakeup-source;
++ access-controllers = <&etzpc 66>;
+ status = "disabled";
+
+ pwm {
+@@ -1461,6 +1513,7 @@
+ clocks = <&rcc LPTIM5_K>;
+ clock-names = "mux";
+ wakeup-source;
++ access-controllers = <&etzpc 67>;
+ status = "disabled";
+
+ pwm {
+@@ -1476,6 +1529,7 @@
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <2500000>;
+ clocks = <&rcc VREF>;
++ access-controllers = <&etzpc 69>;
+ status = "disabled";
+ };
+
+@@ -1487,6 +1541,7 @@
+ reg = <0x50027000 0x4>, <0x500273f0 0x10>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc SAI4_R>;
++ access-controllers = <&etzpc 68>;
+ status = "disabled";
+
+ sai4a: audio-controller@50027004 {
+@@ -1519,6 +1574,7 @@
+ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
+ dma-names = "in";
+ dma-maxburst = <2>;
++ access-controllers = <&etzpc 8>;
+ status = "disabled";
+ };
+
+@@ -1527,6 +1583,7 @@
+ reg = <0x54003000 0x400>;
+ clocks = <&rcc RNG1_K>;
+ resets = <&rcc RNG1_R>;
++ access-controllers = <&etzpc 7>;
+ status = "disabled";
+ };
+
+@@ -1537,6 +1594,7 @@
+ reg = <0x58002000 0x1000>;
+ clocks = <&rcc FMC_K>;
+ resets = <&rcc FMC_R>;
++ access-controllers = <&etzpc 91>;
+ status = "disabled";
+
+ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+@@ -1576,6 +1634,7 @@
+ resets = <&rcc QSPI_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
++ access-controllers = <&etzpc 92>;
+ status = "disabled";
+ };
+
+@@ -1603,6 +1662,7 @@
+ snps,en-tx-lpi-clockgating;
+ snps,axi-config = <&stmmac_axi_config_0>;
+ snps,tso;
++ access-controllers = <&etzpc 94>;
+ status = "disabled";
+
+ stmmac_axi_config_0: stmmac-axi-config {
+@@ -1618,6 +1678,7 @@
+ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART1_K>;
+ wakeup-source;
++ access-controllers = <&etzpc 3>;
+ status = "disabled";
+ };
+
+@@ -1631,6 +1692,7 @@
+ resets = <&rcc SPI6_R>;
+ dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
+ <&mdma1 35 0x0 0x40002 0x0 0x0>;
++ access-controllers = <&etzpc 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+@@ -1648,6 +1710,7 @@
+ st,syscfg-fmp = <&syscfg 0x4 0x8>;
+ wakeup-source;
+ i2c-analog-filter;
++ access-controllers = <&etzpc 5>;
+ status = "disabled";
+ };
+
+@@ -1664,6 +1727,7 @@
+ st,syscfg-fmp = <&syscfg 0x4 0x20>;
+ wakeup-source;
+ i2c-analog-filter;
++ access-controllers = <&etzpc 12>;
+ status = "disabled";
+ };
+ };
+--- a/arch/arm/boot/dts/st/stm32mp153.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp153.dtsi
+@@ -41,6 +41,7 @@
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
++ access-controllers = <&etzpc 62>;
+ status = "disabled";
+ };
+
+@@ -54,6 +55,7 @@
+ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
++ access-controllers = <&etzpc 62>;
+ status = "disabled";
+ };
+ };
+--- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi
+@@ -11,6 +11,7 @@
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc CRYP1>;
+ resets = <&rcc CRYP1_R>;
++ access-controllers = <&etzpc 9>;
+ status = "disabled";
+ };
+ };
--- /dev/null
+From 1bcfbfd7c9aa716f61a01682345a1b329f6a6e66 Mon Sep 17 00:00:00 2001
+Date: Wed, 8 Nov 2023 15:16:37 +0100
+Subject: [PATCH] mmc: mmci: stm32: add SDIO in-band interrupt mode
+
+Add the support of SDIO in-band interrupt mode for STM32 and Ux500
+variants.
+It allows the SD I/O card to interrupt the host on SDMMC_D1 data line.
+It is not enabled by default on Ux500 variant as this is unstable and
+Ux500 users should use out-of-band IRQs.
+
+---
+ drivers/mmc/host/mmci.c | 69 +++++++++++++++++++++++++++++++++++++++--
+ drivers/mmc/host/mmci.h | 2 ++
+ 2 files changed, 69 insertions(+), 2 deletions(-)
+
+--- a/drivers/mmc/host/mmci.c
++++ b/drivers/mmc/host/mmci.c
+@@ -272,6 +272,7 @@ static struct variant_data variant_stm32
+ .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
+ .stm32_idmabsize_mask = GENMASK(12, 5),
+ .stm32_idmabsize_align = BIT(5),
++ .supports_sdio_irq = true,
+ .busy_timeout = true,
+ .busy_detect = true,
+ .busy_detect_flag = MCI_STM32_BUSYD0,
+@@ -299,6 +300,7 @@ static struct variant_data variant_stm32
+ .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
+ .stm32_idmabsize_mask = GENMASK(16, 5),
+ .stm32_idmabsize_align = BIT(5),
++ .supports_sdio_irq = true,
+ .dma_lli = true,
+ .busy_timeout = true,
+ .busy_detect = true,
+@@ -327,6 +329,7 @@ static struct variant_data variant_stm32
+ .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
+ .stm32_idmabsize_mask = GENMASK(16, 6),
+ .stm32_idmabsize_align = BIT(6),
++ .supports_sdio_irq = true,
+ .dma_lli = true,
+ .busy_timeout = true,
+ .busy_detect = true,
+@@ -420,8 +423,9 @@ void mmci_write_pwrreg(struct mmci_host
+ */
+ static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
+ {
+- /* Keep busy mode in DPSM if enabled */
+- datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
++ /* Keep busy mode in DPSM and SDIO mask if enabled */
++ datactrl |= host->datactrl_reg & (host->variant->busy_dpsm_flag |
++ host->variant->datactrl_mask_sdio);
+
+ if (host->datactrl_reg != datactrl) {
+ host->datactrl_reg = datactrl;
+@@ -1761,6 +1765,25 @@ static irqreturn_t mmci_pio_irq(int irq,
+ return IRQ_HANDLED;
+ }
+
++static void mmci_write_sdio_irq_bit(struct mmci_host *host, int enable)
++{
++ void __iomem *base = host->base;
++ u32 mask = readl_relaxed(base + MMCIMASK0);
++
++ if (enable)
++ writel_relaxed(mask | MCI_ST_SDIOITMASK, base + MMCIMASK0);
++ else
++ writel_relaxed(mask & ~MCI_ST_SDIOITMASK, base + MMCIMASK0);
++}
++
++static void mmci_signal_sdio_irq(struct mmci_host *host, u32 status)
++{
++ if (status & MCI_ST_SDIOIT) {
++ mmci_write_sdio_irq_bit(host, 0);
++ sdio_signal_irq(host->mmc);
++ }
++}
++
+ /*
+ * Handle completion of command and data transfers.
+ */
+@@ -1805,6 +1828,9 @@ static irqreturn_t mmci_irq(int irq, voi
+ mmci_data_irq(host, host->data, status);
+ }
+
++ if (host->variant->supports_sdio_irq)
++ mmci_signal_sdio_irq(host, status);
++
+ /*
+ * Busy detection has been handled by mmci_cmd_irq() above.
+ * Clear the status bit to prevent polling in IRQ context.
+@@ -2041,6 +2067,35 @@ static int mmci_sig_volt_switch(struct m
+ return ret;
+ }
+
++static void mmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
++{
++ struct mmci_host *host = mmc_priv(mmc);
++ unsigned long flags;
++
++ if (enable)
++ /* Keep the SDIO mode bit if SDIO irqs are enabled */
++ pm_runtime_get_sync(mmc_dev(mmc));
++
++ spin_lock_irqsave(&host->lock, flags);
++ mmci_write_sdio_irq_bit(host, enable);
++ spin_unlock_irqrestore(&host->lock, flags);
++
++ if (!enable) {
++ pm_runtime_mark_last_busy(mmc_dev(mmc));
++ pm_runtime_put_autosuspend(mmc_dev(mmc));
++ }
++}
++
++static void mmci_ack_sdio_irq(struct mmc_host *mmc)
++{
++ struct mmci_host *host = mmc_priv(mmc);
++ unsigned long flags;
++
++ spin_lock_irqsave(&host->lock, flags);
++ mmci_write_sdio_irq_bit(host, 1);
++ spin_unlock_irqrestore(&host->lock, flags);
++}
++
+ static struct mmc_host_ops mmci_ops = {
+ .request = mmci_request,
+ .pre_req = mmci_pre_request,
+@@ -2316,6 +2371,16 @@ static int mmci_probe(struct amba_device
+ mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+ }
+
++ if (variant->supports_sdio_irq && host->mmc->caps & MMC_CAP_SDIO_IRQ) {
++ mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
++
++ mmci_ops.enable_sdio_irq = mmci_enable_sdio_irq;
++ mmci_ops.ack_sdio_irq = mmci_ack_sdio_irq;
++
++ mmci_write_datactrlreg(host,
++ host->variant->datactrl_mask_sdio);
++ }
++
+ /* Variants with mandatory busy timeout in HW needs R1B responses. */
+ if (variant->busy_timeout)
+ mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
+--- a/drivers/mmc/host/mmci.h
++++ b/drivers/mmc/host/mmci.h
+@@ -331,6 +331,7 @@ enum mmci_busy_state {
+ * register.
+ * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
+ * @dma_lli: true if variant has dma link list feature.
++ * @supports_sdio_irq: allow SD I/O card to interrupt the host
+ * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
+ */
+ struct variant_data {
+@@ -376,6 +377,7 @@ struct variant_data {
+ u32 start_err;
+ u32 opendrain;
+ u8 dma_lli:1;
++ bool supports_sdio_irq;
+ u32 stm32_idmabsize_mask;
+ u32 stm32_idmabsize_align;
+ void (*init)(struct mmci_host *host);
u32 speed;
const struct stm32_ops *ops;
struct device *dev;
-@@ -374,6 +376,16 @@ static int stm32_dwmac_parse_data(struct
- dev_dbg(dev, "Warning sysconfig register mask not set\n");
+@@ -379,6 +381,16 @@ static int stm32_dwmac_parse_data(struct
+ }
}
+ dwmac->regulator = devm_regulator_get_optional(dev, "phy");
return err;
}
-@@ -439,6 +451,28 @@ static int stm32mp1_parse_data(struct st
+@@ -444,6 +456,28 @@ static int stm32mp1_parse_data(struct st
return err;
}
static int stm32_dwmac_probe(struct platform_device *pdev)
{
struct plat_stmmacenet_data *plat_dat;
-@@ -480,12 +514,18 @@ static int stm32_dwmac_probe(struct plat
+@@ -485,12 +519,18 @@ static int stm32_dwmac_probe(struct plat
if (ret)
return ret;
err_clk_disable:
stm32_dwmac_clk_disable(dwmac, false);
-@@ -506,6 +546,8 @@ static void stm32_dwmac_remove(struct pl
+@@ -511,6 +551,8 @@ static void stm32_dwmac_remove(struct pl
dev_pm_clear_wake_irq(&pdev->dev);
device_init_wakeup(&pdev->dev, false);
}
--- /dev/null
+From 6e10eb83e20e3a31bef8580bb4197240b0a28888 Mon Sep 17 00:00:00 2001
+Date: Thu, 17 Oct 2024 19:51:32 +0200
+Subject: [PATCH] ARM: dts: stm32: add missing eth_wake_irq interrupt for the
+ ethernet on STM32MP157
+
+---
+ arch/arm/boot/dts/st/stm32mp151.dtsi | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/st/stm32mp151.dtsi
++++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
+@@ -1642,8 +1642,10 @@
+ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
+ reg = <0x5800a000 0x2000>;
+ reg-names = "stmmaceth";
+- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "macirq";
++ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
++ <&exti 70 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq",
++ "eth_wake_irq";
+ clock-names = "stmmaceth",
+ "mac-clk-tx",
+ "mac-clk-rx",
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_STM32MP135=y
+CONFIG_COMMON_CLK_STM32MP157=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_HW_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_OPTEE=y
-# CONFIG_HW_RANDOM_STM32 is not set
+CONFIG_HW_RANDOM_STM32=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_STM32F4 is not set
CONFIG_I2C_STM32F7=y
CONFIG_INPUT=y
+# CONFIG_INPUT_STPMIC1_ONKEY is not set
# CONFIG_IOMMUFD is not set
# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_IO_PGTABLE=y
# CONFIG_LRU_GEN is not set
CONFIG_LZO_DECOMPRESS=y
CONFIG_MACH_STM32MP13=y
-# CONFIG_MACH_STM32MP157 is not set
+CONFIG_MACH_STM32MP157=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MDIO_BITBANG=y
# CONFIG_MDIO_GPIO is not set
CONFIG_MEMORY=y
CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_CORE=y
# CONFIG_MFD_STM32_LPTIMER is not set
# CONFIG_MFD_STM32_TIMERS is not set
+CONFIG_MFD_STPMIC1=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_PINCTRL_MCP23S08_I2C=y
CONFIG_PINCTRL_STM32=y
CONFIG_PINCTRL_STM32MP135=y
+CONFIG_PINCTRL_STM32MP157=y
# CONFIG_PL353_SMC is not set
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
# CONFIG_RAVE_SP_CORE is not set
+CONFIG_REALTEK_PHY=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_ARM_SCMI=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
# CONFIG_REGULATOR_STM32_BOOSTER is not set
-# CONFIG_REGULATOR_STM32_PWR is not set
+CONFIG_REGULATOR_STM32_PWR=y
# CONFIG_REGULATOR_STM32_VREFBUF is not set
+CONFIG_REGULATOR_STPMIC1=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SCMI=y
CONFIG_RESET_SIMPLE=y
CONFIG_STM32_WATCHDOG=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_PLATFORM=y
+# CONFIG_STPMIC1_WATCHDOG is not set
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
projects / openwrt / staging / linusw.git / commitdiff