MIPS: Allow UserLocal on MIPS_R1 processors

Some MIPS32R1 processors implement UserLocal (RDHWR $29) to accelerate
programs that make extensive use of thread-local storage.  Therefore,
setting up the HWRENA register should not depend on cpu_has_mips_r2.

Signed-off-by: Kevin Cernekee <[email protected]>
Cc: [email protected]
Cc: [email protected]

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 8d79b8774b3088346de38be0d23bfa1032f15686..8e9fbe75894e5f5199618264fcddde6410d42dc7 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1481,6 +1481,7 @@ void __cpuinit per_cpu_trap_init(void)
 {
        unsigned int cpu = smp_processor_id();
        unsigned int status_set = ST0_CU0;
+       unsigned int hwrena = cpu_hwrena_impl_bits;
 #ifdef CONFIG_MIPS_MT_SMTC
        int secondaryTC = 0;
        int bootTC = (cpu == 0);
@@ -1513,14 +1514,14 @@ void __cpuinit per_cpu_trap_init(void)
        change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
                         status_set);
 
-       if (cpu_has_mips_r2) {
-               unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
+       if (cpu_has_mips_r2)
+               hwrena |= 0x0000000f;
 
-               if (!noulri && cpu_has_userlocal)
-                       enable |= (1 << 29);
+       if (!noulri && cpu_has_userlocal)
+               hwrena |= (1 << 29);
 
-               write_c0_hwrena(enable);
-       }
+       if (hwrena)
+               write_c0_hwrena(hwrena);
 
 #ifdef CONFIG_MIPS_MT_SMTC
        if (!secondaryTC) {