Hikey960: configure pins for PCIe controller

GPIO_089 connects to PCIE_PERST_N. It needs to be configured as
output low.

Signed-off-by: Kaihua Zhong <[email protected]>
Signed-off-by: Xiaowei Song <[email protected]>
Signed-off-by: Haojian Zhuang <[email protected]>

diff --git a/plat/hisilicon/hikey960/hikey960_bl1_setup.c b/plat/hisilicon/hikey960/hikey960_bl1_setup.c
index 6a07f092449788c4cd06587aaa619a0f597efb3e..a92857659102dd921cc2b6872d9a03c1f08ef273 100644 (file)
--- a/plat/hisilicon/hikey960/hikey960_bl1_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl1_setup.c
@@ -211,6 +211,7 @@ void bl1_platform_setup(void)
        hikey960_peri_init();
        hikey960_ufs_init();
        hikey960_pinmux_init();
+       hikey960_gpio_init();
        hikey960_io_setup();
 }
 

diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c
index 6e726d2f521249ceb7c3bcd1c5ff1fb608737d5f..f57dd63ce2dc7ba0275f5ec77131545db0dd33ff 100644 (file)
--- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c
@@ -328,6 +328,7 @@ void bl2_platform_setup(void)
        hikey960_tzc_init();
        hikey960_peri_init();
        hikey960_pinmux_init();
+       hikey960_gpio_init();
        hikey960_init_ufs();
        hikey960_io_setup();
 }

diff --git a/plat/hisilicon/hikey960/hikey960_bl_common.c b/plat/hisilicon/hikey960/hikey960_bl_common.c
index f192c1e0ec2118ea1c351d04ebc0e0dcdcd0562e..0cee69f94d7f33464048fe79ff2ca348a0e5d5e6 100644 (file)
--- a/plat/hisilicon/hikey960/hikey960_bl_common.c
+++ b/plat/hisilicon/hikey960/hikey960_bl_common.c
@@ -8,6 +8,7 @@
 #include <delay_timer.h>
 #include <hi3660.h>
 #include <mmio.h>
+#include <pl061_gpio.h>
 
 #include "hikey960_private.h"
 
@@ -439,3 +440,34 @@ void hikey960_pinmux_init(void)
        /* GPIO213 - PCIE_CLKREQ_N */
        mmio_write_32(IOMG_AO_033_REG, 1);
 }
+
+void hikey960_gpio_init(void)
+{
+       pl061_gpio_init();
+       pl061_gpio_register(GPIO0_BASE, 0);
+       pl061_gpio_register(GPIO1_BASE, 1);
+       pl061_gpio_register(GPIO2_BASE, 2);
+       pl061_gpio_register(GPIO3_BASE, 3);
+       pl061_gpio_register(GPIO4_BASE, 4);
+       pl061_gpio_register(GPIO5_BASE, 5);
+       pl061_gpio_register(GPIO6_BASE, 6);
+       pl061_gpio_register(GPIO7_BASE, 7);
+       pl061_gpio_register(GPIO8_BASE, 8);
+       pl061_gpio_register(GPIO9_BASE, 9);
+       pl061_gpio_register(GPIO10_BASE, 10);
+       pl061_gpio_register(GPIO11_BASE, 11);
+       pl061_gpio_register(GPIO12_BASE, 12);
+       pl061_gpio_register(GPIO13_BASE, 13);
+       pl061_gpio_register(GPIO14_BASE, 14);
+       pl061_gpio_register(GPIO15_BASE, 15);
+       pl061_gpio_register(GPIO16_BASE, 16);
+       pl061_gpio_register(GPIO17_BASE, 17);
+       pl061_gpio_register(GPIO18_BASE, 18);
+       pl061_gpio_register(GPIO19_BASE, 19);
+       pl061_gpio_register(GPIO20_BASE, 20);
+       pl061_gpio_register(GPIO21_BASE, 21);
+
+       /* PCIE_PERST_N output low */
+       gpio_set_direction(89, GPIO_DIR_OUT);
+       gpio_set_value(89, GPIO_LEVEL_LOW);
+}

diff --git a/plat/hisilicon/hikey960/hikey960_private.h b/plat/hisilicon/hikey960/hikey960_private.h
index 30166e56d0438b4ada24aa6651431e8135388e88..e2425fcadf4c18d5e9e798e225a53a6fab1d1047 100644 (file)
--- a/plat/hisilicon/hikey960/hikey960_private.h
+++ b/plat/hisilicon/hikey960/hikey960_private.h
@@ -32,6 +32,7 @@ void hikey960_regulator_enable(void);
 void hikey960_tzc_init(void);
 void hikey960_peri_init(void);
 void hikey960_pinmux_init(void);
+void hikey960_gpio_init(void);
 void set_retention_ticks(unsigned int val);
 void clr_retention_ticks(unsigned int val);
 void clr_ex(void);

diff --git a/plat/hisilicon/hikey960/include/hi3660.h b/plat/hisilicon/hikey960/include/hi3660.h
index ab7b8aa4688eea02acd77222b290eb4c45982c1c..61b80b0560bd985544d8c54e3bd9639dd58dfb9b 100644 (file)
--- a/plat/hisilicon/hikey960/include/hi3660.h
+++ b/plat/hisilicon/hikey960/include/hi3660.h
@@ -240,6 +240,27 @@
 #define PCTRL_PERI_CTRL3_REG           (PCTRL_REG_BASE + 0x010)
 #define PCTRL_PERI_CTRL24_REG          (PCTRL_REG_BASE + 0x064)
 
+#define GPIO0_BASE                     UL(0xE8A0B000)
+#define GPIO1_BASE                     UL(0xE8A0C000)
+#define GPIO2_BASE                     UL(0xE8A0D000)
+#define GPIO3_BASE                     UL(0xE8A0E000)
+#define GPIO4_BASE                     UL(0xE8A0F000)
+#define GPIO5_BASE                     UL(0xE8A10000)
+#define GPIO6_BASE                     UL(0xE8A11000)
+#define GPIO7_BASE                     UL(0xE8A12000)
+#define GPIO8_BASE                     UL(0xE8A13000)
+#define GPIO9_BASE                     UL(0xE8A14000)
+#define GPIO10_BASE                    UL(0xE8A15000)
+#define GPIO11_BASE                    UL(0xE8A16000)
+#define GPIO12_BASE                    UL(0xE8A17000)
+#define GPIO13_BASE                    UL(0xE8A18000)
+#define GPIO14_BASE                    UL(0xE8A19000)
+#define GPIO15_BASE                    UL(0xE8A1A000)
+#define GPIO16_BASE                    UL(0xE8A1B000)
+#define GPIO17_BASE                    UL(0xE8A1C000)
+#define GPIO20_BASE                    UL(0xE8A1F000)
+#define GPIO21_BASE                    UL(0xE8A20000)
+
 #define TZC_REG_BASE                   0xE8A21000
 #define TZC_STAT0_REG                  (TZC_REG_BASE + 0x800)
 #define TZC_EN0_REG                    (TZC_REG_BASE + 0x804)
@@ -316,6 +337,9 @@
 #define MASK_UFS_DEVICE_RESET                  (1 << 16)
 #define BIT_UFS_DEVICE_RESET                   (1 << 0)
 
+#define GPIO18_BASE                    UL(0xFF3B4000)
+#define GPIO19_BASE                    UL(0xFF3B5000)
+
 #define IOMG_FIX_REG_BASE              0xFF3B6000
 
 /* GPIO150: LED */

diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk
index 8b03e555db63183346a91c8791aba35eb2cd5dee..5fa7218421e97f91c7b0e0e3c9ae303cc92a3ff0 100644 (file)
--- a/plat/hisilicon/hikey960/platform.mk
+++ b/plat/hisilicon/hikey960/platform.mk
@@ -22,12 +22,14 @@ endif
 
 CRASH_CONSOLE_BASE             :=      PL011_UART6_BASE
 COLD_BOOT_SINGLE_CPU           :=      1
+PLAT_PL061_MAX_GPIOS           :=      176
 PROGRAMMABLE_RESET_ADDRESS     :=      1
 ENABLE_SVE_FOR_NS              :=      0
 
 # Process flags
 $(eval $(call add_define,HIKEY960_TSP_RAM_LOCATION_ID))
 $(eval $(call add_define,CRASH_CONSOLE_BASE))
+$(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
 
 # Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
 # in the FIP if the platform requires.
@@ -58,6 +60,8 @@ HIKEY960_GIC_SOURCES  :=      drivers/arm/gic/common/gic_common.c     \
                                plat/common/plat_gicv2.c
 
 BL1_SOURCES            +=      bl1/tbbr/tbbr_img_desc.c                \
+                               drivers/arm/pl061/pl061_gpio.c          \
+                               drivers/gpio/gpio.c                     \
                                drivers/io/io_block.c                   \
                                drivers/io/io_fip.c                     \
                                drivers/io/io_storage.c                 \
@@ -71,6 +75,8 @@ BL1_SOURCES           +=      bl1/tbbr/tbbr_img_desc.c                \
                                ${HIKEY960_GIC_SOURCES}
 
 BL2_SOURCES            +=      common/desc_image_load.c                \
+                               drivers/arm/pl061/pl061_gpio.c          \
+                               drivers/gpio/gpio.c                     \
                                drivers/io/io_block.c                   \
                                drivers/io/io_fip.c                     \
                                drivers/io/io_storage.c                 \