riscv: save hart ID in register tp instead of s0

The hart ID passed by the previous boot stage is currently stored in
register s0. If we divert the control flow inside a function, which is
required as part of multi-hart support, the function epilog may not be
called, clobbering register s0. Save the hart ID in the unallocatable
register tp instead to protect the hart ID.

Signed-off-by: Lukas Auer <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
Reviewed-by: Anup Patel <[email protected]>

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a30f6f7194772c46e158c016a1e0b7d71a004d52..bcc0ff696dc11fc5708c5e7ac9017d0632914b47 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -36,7 +36,7 @@
 .globl _start
 _start:
        /* save hart id and dtb pointer */
-       mv      s0, a0
+       mv      tp, a0
        mv      s1, a1
 
        la      t0, trap_entry
@@ -64,7 +64,7 @@ call_board_init_f_0:
        jal     board_init_f_init_reserve
 
        /* save the boot hart id to global_data */
-       SREG    s0, GD_BOOT_HART(gp)
+       SREG    tp, GD_BOOT_HART(gp)
 
        /* Enable cache */
        jal     icache_enable