drm/i915/guc: write wopcm related register once during uc init

The wopcm registers are write-once, so any write after the first one
will just be ignored. The registers survive a GPU reset but not
always a suspend/resume cycle, so to keep things simple keep the
writes in the intel_uc_init_hw function instead of moving it earlier
to make sure we attempt them every time we try to load GuC.

Cc: Jeff McGee <[email protected]>
Cc: Anusha Srivatsa <[email protected]>
Signed-off-by: Daniele Ceraolo Spurio <[email protected]>
Reviewed-by: Joonas Lahtinen <[email protected]>
Signed-off-by: Joonas Lahtinen <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/1491524332-23860-1-git-send-email-daniele.ceraolospurio@intel.com

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 12f80ece1d0527a999b2a145af1df516cccefc42..d9045b6e897b4b3a2b77f6fad411a9a180f297d4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -285,10 +285,6 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 
        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
-       /* init WOPCM */
-       I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
-       I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
-
        /* Enable MIA caching. GuC clock gating is disabled. */
        I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 

diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 7a0bf1593463cabd2bc897f523351cb15377673d..88b4cf3f764a23d3118de02fdc4029eff8e0594d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -106,11 +106,6 @@ static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
 
        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
-       /* init WOPCM */
-       I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
-       I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE |
-                       HUC_LOADING_AGENT_GUC);
-
        /* Set the source address for the uCode */
        offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
        I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 4364b1a9064ebd12e7b5dc823860ee91701a178a..900e3767a899c3e6a074db4267afbedff716be11 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -274,6 +274,11 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
                        goto err_guc;
        }
 
+       /* init WOPCM */
+       I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
+       I915_WRITE(DMA_GUC_WOPCM_OFFSET,
+                  GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
+
        /* WaEnableuKernelHeaderValidFix:skl */
        /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
        if (IS_GEN9(dev_priv))