arm: Implement workaround for Cortex-A9 errata 845369

Under very rare timing circumstances, transitioning into streaming
mode might create a data corruption. Present on Two or more processors
or 1 core with ACP, all revisions. This erratum can be worked round
by setting bit[22] of the undocumented Diagnostic Control Register to 1.

Signed-off-by: Peng Fan <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7f6ab4ac7e6e77238019e146bc1b571bbfc83446..787f2b14a8ee19deba8c3f970a89e3cfb9cf15aa 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -97,6 +97,9 @@ config ARM_ERRATA_833069
 config ARM_ERRATA_833471
        bool
 
+config ARM_ERRATA_845369
+       bool
+
 config ARM_ERRATA_852421
        bool
 

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index f06fd28940e7700d9e70779f21c9fa7a6937f38d..7b84a7a0f161207611202c7f44544208c70fed13 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -187,6 +187,12 @@ ENTRY(cpu_init_cp15)
        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 #endif
 
+#ifdef CONFIG_ARM_ERRATA_845369
+       mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
+       orr     r0, r0, #1 << 22        @ set bit #22
+       mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+#endif
+
        mov     r5, lr                  @ Store my Caller
        mrc     p15, 0, r1, c0, c0, 0   @ r1 has Read Main ID Register (MIDR)
        mov     r3, r1, lsr #20         @ get variant field