drm/i915: Use simplest form for flushing the single cacheline in the HWS

Rather than call a function to compute the matching cachelines and
clflush them, just call the clflush *instruction* directly. We also know
that we can use the unpatched plain clflush rather than the clflushopt
alternative.

Signed-off-by: Chris Wilson <[email protected]>
Cc: Mika Kuoppala <[email protected]>
Cc: Imre Deak <[email protected]>
Reviewed-by: Mika Kuoppala <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 29c54cc1ee5cf06bc9d3d83da8c797317c974b5a..9d7b7bf9ed14a49f802f5cfdec7a3162222e5a3e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -385,8 +385,9 @@ intel_ring_sync_index(struct intel_engine_cs *engine,
 static inline void
 intel_flush_status_page(struct intel_engine_cs *engine, int reg)
 {
-       drm_clflush_virt_range(&engine->status_page.page_addr[reg],
-                              sizeof(uint32_t));
+       mb();
+       clflush(&engine->status_page.page_addr[reg]);
+       mb();
 }
 
 static inline u32