perf/x86/intel/cqm: Avoid pointless MSR write

If the usage counter is non-zero there is no point to update the rmid
in the PQR MSR.

Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Acked-by: Matt Fleming <[email protected]>
Cc: Kanaka Juvva <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Vikas Shivappa <[email protected]>
Cc: Will Auld <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>

diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
index 63391f860175bcd6bc4dee4b47b7d55bec9c3a1c..2ce69c0953abe10f9d943de827aa8953d1a466b5 100644 (file)
--- a/arch/x86/kernel/cpu/perf_event_intel_cqm.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
@@ -974,10 +974,12 @@ static void intel_cqm_event_start(struct perf_event *event, int mode)
 
        event->hw.cqm_state &= ~PERF_HES_STOPPED;
 
-       if (state->cnt++)
-               WARN_ON_ONCE(state->rmid != rmid);
-       else
+       if (state->cnt++) {
+               if (!WARN_ON_ONCE(state->rmid != rmid))
+                       return;
+       } else {
                WARN_ON_ONCE(state->rmid);
+       }
 
        state->rmid = rmid;
        /*