plat/intel: Fix SMPLSEL for MMC

MMC sample select needs to be set properly so that DWMMC clock can be
driven to 50Mhz

Signed-off-by: Tien Hock, Loh <[email protected]>
Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a

diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h
index 802386c8e29ae164f7cc9ffea929fb7c96ffe98d..4500c6fbd1932465cb58d64af9cb9b9af674aaf7 100644 (file)
--- a/plat/intel/soc/stratix10/include/s10_system_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_system_manager.h
@@ -59,6 +59,11 @@
 #define S10_CCU_NOC_CPU0_RAMSPACE0_0           0xf7004688
 #define S10_CCU_NOC_IOM_RAMSPACE0_0            0xf7018628
 
+#define S10_SYSMGR_CORE(x)                     (0xffd12000 + (x))
+#define SYSMGR_MMC                             0x28
+#define SYSMGR_MMC_DRVSEL(x)                   (((x) & 0x7) << 0)
+
+
 #define DISABLE_L4_FIREWALL    (BIT(0) | BIT(16) | BIT(24))
 
 void enable_nonsecure_access(void);

diff --git a/plat/intel/soc/stratix10/soc/s10_system_manager.c b/plat/intel/soc/stratix10/soc/s10_system_manager.c
index 48f37d78d12d41ef2dbe20f411d3b4d88f72346a..a2ed5a3edb43df15fac7ca1181d7f8de43c82ef4 100644 (file)
--- a/plat/intel/soc/stratix10/soc/s10_system_manager.c
+++ b/plat/intel/soc/stratix10/soc/s10_system_manager.c
@@ -86,5 +86,8 @@ void enable_nonsecure_access(void)
 
        mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
        mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
+
+       mmio_write_32(S10_SYSMGR_CORE(SYSMGR_MMC), SYSMGR_MMC_DRVSEL(3));
+
 }