drm/i915: Update cached cdclk state from broxton_init_cdclk()

Let's make sure our cached cdclk state is accurate right after
broxton_init_cdclk() whether or not we end up changing the cdclk
frequency.

Signed-off-by: Ville Syrjälä <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Imre Deak <[email protected]>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6382241cb7870ec68db9aa6f8eabca3487eeb762..4dfeb6ebc0154ccc7bc3ba5099d96e09e51bc01d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5428,13 +5428,10 @@ bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
 
 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 {
-       /* check if cd clock is enabled */
-       if (broxton_cdclk_is_enabled(dev_priv)) {
-               DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
-               return;
-       }
+       intel_update_cdclk(dev_priv->dev);
 
-       DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
+       if (dev_priv->cdclk_pll.vco != 0)
+               return;
 
        /*
         * FIXME: