MIPS: DB1200: Set Config[OD] for improved stability.

Setting Config[OD] gets rid of a _LOT_ of spurious CPLD interrupts,
but also decreases overall performance a bit.

Signed-off-by: Manuel Lauss <[email protected]>
To: Linux-MIPS <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Wolfgang Grandegger <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/2347/
Signed-off-by: Ralf Baechle <[email protected]>

diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 561e5da2658b36f999c6da9bc8377c9f0b203289..1b887c86841754133e2539a2e5f4c9748ed2e7df 100644 (file)
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -52,8 +52,6 @@ void __init plat_mem_setup(void)
        /* this is faster than wasting cycles trying to approximate it */
        preset_lpj = (est_freq >> 1) / HZ;
 
-       board_setup();  /* board specific setup */
-
        if (au1xxx_cpu_needs_config_od())
                /* Various early Au1xx0 errata corrected by this */
                set_c0_config(1 << 19); /* Set Config[OD] */
@@ -61,6 +59,8 @@ void __init plat_mem_setup(void)
                /* Clear to obtain best system bus performance */
                clear_c0_config(1 << 19); /* Clear Config[OD] */
 
+       board_setup();  /* board specific setup */
+
        /* IO/MEM resources. */
        set_io_port_base(0);
        ioport_resource.start = IOPORT_RESOURCE_START;

diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
index 4a8980027ecf83538229e71ea67fe3c27c2a4517..1dac4f27d33452e7c572b06f4000bd6a44de232b 100644 (file)
--- a/arch/mips/alchemy/devboards/db1200/setup.c
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -23,6 +23,13 @@ void __init board_setup(void)
        unsigned long freq0, clksrc, div, pfc;
        unsigned short whoami;
 
+       /* Set Config[OD] (disable overlapping bus transaction):
+        * This gets rid of a _lot_ of spurious interrupts (especially
+        * wrt. IDE); but incurs ~10% performance hit in some
+        * cpu-bound applications.
+        */
+       set_c0_config(1 << 19);
+
        bcsr_init(DB1200_BCSR_PHYS_ADDR,
                  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);