MIPS: traps: Make sure secondary cores have a sane ebase register

We shouldn't trust that the secondary cores will have a sane ebase register
(either from the bootloader or during the hardware design phase) so use the
ebase address as calculated by the boot CPU.

Signed-off-by: Markos Chandras <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Leonid Yegoshin <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Petri Gynther <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12328/
Signed-off-by: Ralf Baechle <[email protected]>

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 82c2fcf7e585f8897ee52d611a0e543f2cd85cc8..bd4893feffa6d50672ab19b20c8406956f99315f 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2116,6 +2116,13 @@ void per_cpu_trap_init(bool is_boot_cpu)
         *  o read IntCtl.IPFDC to determine the fast debug channel interrupt
         */
        if (cpu_has_mips_r2_r6) {
+               /*
+                * We shouldn't trust a secondary core has a sane EBASE register
+                * so use the one calculated by the boot CPU.
+                */
+               if (!is_boot_cpu)
+                       write_c0_ebase(ebase);
+
                cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
                cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
                cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;