drm/i915/icl: Add reset control register changes
authorMichel Thierry <[email protected]>
Thu, 5 Apr 2018 14:00:48 +0000 (17:00 +0300)
committerMika Kuoppala <[email protected]>
Fri, 6 Apr 2018 12:33:04 +0000 (15:33 +0300)
commite34b0345e6a531f980a6560fdc3b651de9cfcc67
tree23cab34e8b16b3434a478a930a089eda4b18a0aa
parent99d7e4eeea778374ecea279d0379fbecb0b297bf
drm/i915/icl: Add reset control register changes

The bits used to reset the different engines/domains have changed in
GEN11, this patch maps the reset engine mask bits with the new bits
in the reset control register.

v2: Use shift-left instead of BIT macro to match the file style (Paulo).
v3: Reuse gen8_reset_engines (Daniele).
v4: Do not call intel_uncore_forcewake_reset after reset, we may be
using the forcewake to read protected registers elsewhere and those
results may be clobbered by the concurrent dropping of forcewake.

bspec: 19212
Cc: Oscar Mateo <[email protected]>
Cc: Antonio Argenziano <[email protected]>
Cc: Paulo Zanoni <[email protected]>
Cc: Daniele Ceraolo Spurio <[email protected]>
Acked-by: Daniele Ceraolo Spurio <[email protected]>
Signed-off-by: Michel Thierry <[email protected]>
Reviewed-by: Oscar Mateo <[email protected]>
Signed-off-by: Mika Kuoppala <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_uncore.c