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(parent: 42b3fdf) | patch
ath79: ar913x: fix eth pll register
authorChuanhong Guo <[email protected]>
Sun, 12 Aug 2018 13:13:31 +0000 (21:13 +0800)
committerMathias Kresin <[email protected]>
Mon, 13 Aug 2018 06:37:19 +0000 (08:37 +0200)
commitcf50f720695eb2d9d232a588b5a7f4959ef3fcee
tree8f7a0efe94226da9beb1f30cd2532679636ae156tree | snapshot
parent42b3fdf9812f799c07bd30899a2bb2cff7d1a200commit | diff
ath79: ar913x: fix eth pll register

PLL for eth0 internal clock on ar913x is at 0x18050014
and AR913X_ETH0_PLL_SHIFT is 20 instead of 17

Signed-off-by: Chuanhong Guo <[email protected]>
target/linux/ath79/dts/ar9132.dtsi diff | blob | history
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