projects / openwrt / staging / stintel.git / commit
| author | Chukun Pan <[email protected]> | |
| Tue, 25 Apr 2023 15:06:20 +0000 (23:06 +0800) | ||
| committer | Daniel Golle <[email protected]> | |
| Sat, 27 May 2023 10:01:45 +0000 (11:01 +0100) | ||
| commit | c620409d58a29d49ceccf838e90e030610c06611 | |
| tree | 1bf335d9371e1e87dee132decdc214cede5247eb | tree | snapshot |
| parent | 3eb354f999a3687f9ae547899b0f5ec2b10185ab | commit | diff |
| target/linux/mediatek/image/filogic.mk | diff | blob | history |