Fixup bug in PMIC TPS65217 register address definition
authorBrock Zheng Techyauld Ltd <[email protected]>
Tue, 6 Jun 2017 01:06:21 +0000 (09:06 +0800)
committerJaehoon Chung <[email protected]>
Fri, 9 Jun 2017 11:25:16 +0000 (20:25 +0900)
commitabf54bf978ed9932d69ee7f937012398d0d8d08f
treeabaefb891099fae50bd9f59893e9bc713044d9fe
parent2dd9dc02a3fa1f8c244482e180415d19a5ead929
Fixup bug in PMIC TPS65217 register address definition

The addresses of the registers in TI TPS65217 are not continuous.
     There is a gap between ENABLE(0x16) and DEFUVLO(0x18). No 0x17
     register available.

     Fixup the enum values by adding a 'reserved' placeholder to correct
     the addresses higher than 0x17.

Series-to: Heiko Schocher <[email protected]>
Signed-off-by: Brock Zheng Techyauld Ltd <[email protected]>
Reviewed-by: Lukasz Majewski <[email protected]>
include/power/tps65217.h