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(parent: a35f5c1) | patch
pinctrl: meson: add gen_clk pins
authorJerome Brunet <[email protected]>
Wed, 4 Jul 2018 16:57:24 +0000 (18:57 +0200)
committerLinus Walleij <[email protected]>
Mon, 16 Jul 2018 12:46:11 +0000 (14:46 +0200)
commita130af0162409fc8a118930255979d8be4adde5a
tree0f30ab3634bc6fcf9cadbb3088e587921aeb4373tree | snapshot
parenta35f5c1ac2d4bdd777ffb8883961c10248da2aaecommit | diff
pinctrl: meson: add gen_clk pins

Add the pinctrl configuration for gen_clk on gxbb and axg.
gen_clk allows to output and devide several internal clocks of SoC,
including most of the plls.

Signed-off-by: Jerome Brunet <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
drivers/pinctrl/meson/pinctrl-meson-axg.c diff | blob | history
drivers/pinctrl/meson/pinctrl-meson-gxbb.c diff | blob | history
John Crispins staging tree