drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence

drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence

The condition for setting the Loadgen Select bit of
PORT_TX_DW4 register during DDI Vswing Sequence should be
Bit rate <=6 GHz whereas the existing code checks only
Bit Rate < 6GHz. This patch fixes this condition.
While at it also remove the redundant paranthesis.

Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.")
Cc: Paulo Zanoni <[email protected]>
Cc: Rodrigo Vivi <[email protected]>
Signed-off-by: Manasi Navare <[email protected]>
Reviewed-by: Paulo Zanoni <[email protected]>
Signed-off-by: Paulo Zanoni <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Signed-off-by: Daniel Vetter <[email protected]>
(cherry picked from commit a8e45a1c42d11597e975f3e5f2fe182f90cdaa7f)
Signed-off-by: Daniel Vetter <[email protected]>