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(parent: 44c70b9) | patch
riscv64: add new port
authorZoltan HERPAI <[email protected]>
Sun, 16 Dec 2018 10:05:58 +0000 (11:05 +0100)
committerZoltan HERPAI <[email protected]>
Wed, 29 Jul 2020 16:56:43 +0000 (18:56 +0200)
commit53be157e2682ab29ef6d27234e2a1f8ff19eb40a
treeb36075199d4fb8a7d4a30603c84c6308a9c094f2tree | snapshot
parent44c70b9d8788cd63865a743dd7f4a72eec9c7d2ccommit | diff
riscv64: add new port

RISC-V is a new CPU architecture aimed to be fully free and open. This
target will add support for it, based on 4.19.

Supports running on:
 - HiFive Unleashed (which is the most known devboard for this arch)
 - QEMU (support is available in mainline qemu)
Further devboards are expected given the interest in this new arch.

An SD-card image is generated, where the partitions are required to have
specific type codes. Compared to earlier branches for this target, BBL
support is removed, giving way for OpenSBI.

Signed-off-by: Zoltan HERPAI <[email protected]>
target/linux/riscv64/Makefile [new file with mode: 0644] blob
target/linux/riscv64/base-files/etc/board.d/02_network [new file with mode: 0644] blob
target/linux/riscv64/base-files/etc/inittab [new file with mode: 0644] blob
target/linux/riscv64/base-files/lib/preinit/80_debug [new file with mode: 0644] blob
target/linux/riscv64/config-5.4 [new file with mode: 0644] blob
target/linux/riscv64/image/Config.in [new file with mode: 0644] blob
target/linux/riscv64/image/Makefile [new file with mode: 0644] blob
target/linux/riscv64/image/gen_riscv64_sdcard_img.sh [new file with mode: 0644] blob
target/linux/riscv64/patches/0010-pcie-microsemi-added-support-for-the-Vera-board-root.patch [new file with mode: 0644] blob
Staging tree of Zoltan Herpai