projects / openwrt / staging / ansuel.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 9e2c01e) | patch
mediatek: enable sel_clk for spi-mt65xx
authorFurong Xu <[email protected]>
Fri, 16 Dec 2022 13:13:37 +0000 (21:13 +0800)
committerChuanhong Guo <[email protected]>
Fri, 16 Dec 2022 13:42:02 +0000 (21:42 +0800)
commit335c1e7cfdfd477a1106ca05c96ff8949ecd953f
treeca4707664e0e4ab8a5d7e6083e23f009c006a8catree | snapshot
parent9e2c01e4a6a5c9b7c77fde90306af5f441ef2cb0commit | diff
mediatek: enable sel_clk for spi-mt65xx

Without explicitly enabling sel_clk, clk_disable_unused() will disable
it when boot is done, causing CPU hang on SPI1 register access on MT7986.
Explicitly enable sel_clk to make SPI1 functional.

Signed-off-by: Furong Xu <[email protected]>
Signed-off-by: Chuanhong Guo <[email protected]>
target/linux/mediatek/patches-5.15/930-spi-mt65xx-enable-sel-clk.patch [new file with mode: 0644] blob
Staging tree of Christian Marangi