EDAC, altera: Refactor for Altera CycloneV SoC
authorThor Thayer <[email protected]>
Thu, 4 Jun 2015 14:28:46 +0000 (09:28 -0500)
committerBorislav Petkov <[email protected]>
Wed, 24 Jun 2015 16:16:08 +0000 (18:16 +0200)
commit143f4a5ac5af82a4055100c8f40b26187d5c20ba
treeac65223b91db64f2823deefd7552f23e1d9ba116
parentf9ae487e04370e229a96c83a8c86510299712192
EDAC, altera: Refactor for Altera CycloneV SoC

The Arria10 SoC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
for the CycloneV/ArriaV SoCs in preparation for the Arria10 support.

Signed-off-by: Thor Thayer <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: linux-edac <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Borislav Petkov <[email protected]>
drivers/edac/altera_edac.c
drivers/edac/altera_edac.h [new file with mode: 0644]