include: move generic riscv64 ISA to rv64gc
authorZoltan HERPAI <[email protected]>
Mon, 24 Feb 2025 12:18:01 +0000 (12:18 +0000)
committerZoltan HERPAI <[email protected]>
Sun, 13 Apr 2025 14:43:31 +0000 (16:43 +0200)
commit143569c2ed31b8baa0c97ff3b3681fd3a7d506cc
tree4edd3f1c914d24f670a45074b473eafea98b6bcd
parent8cb7919a137b4f2b1a207b43ecbac2af49937f24
include: move generic riscv64 ISA to rv64gc

The current CFLAGS (rv64imafdc) for the riscv64 targets do not contain
the full generic compute extension (g), as that also includes the
zicsr and zifencei extensions/instructions. Rename the default ISA to
'generic' to add distinction to the current binaries (although it's very
minimal), and use rv64gc for CFLAGS.

This is also a prep step for the upcoming gcv (vector-extension supporting)
targets like the Spacemit K1, and the thead-cores like the TH1520.

Compile-tested: all riscv64 targets
Runtime-tested:
 - SiFive Unleashed (FU540)
 - SiFive Unmatched (FU740)
 - Nezha D1 (D1)
 - VisionFive2 (JH7110)

Link: https://github.com/openwrt/openwrt/pull/18094
Tested-by: Chuanhong Guo <[email protected]> # siflower target
Signed-off-by: Zoltan HERPAI <[email protected]>
include/target.mk