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Workaround for Neoverse N1 erratum 1262888
authorlauwal01 <[email protected]>
Mon, 24 Jun 2019 16:47:30 +0000 (11:47 -0500)
committerlauwal01 <[email protected]>
Tue, 2 Jul 2019 14:17:17 +0000 (09:17 -0500)
commit11c48370bd8c1dfdf5221a073a26615904c94413
tree00db093dd1481dc07924f494580abf82f326554btree | snapshot
parent411f4959b45b7a072b567dadf33b110936f14f32commit | diff
Workaround for Neoverse N1 erratum 1262888

Neoverse N1 erratum 1262888 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined
CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html

Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105
Signed-off-by: Lauren Wehrmeister <[email protected]>
docs/design/cpu-specific-build-macros.rst diff | blob | history
include/lib/cpus/aarch64/neoverse_n1.h diff | blob | history
lib/cpus/aarch64/neoverse_n1.S diff | blob | history
lib/cpus/cpu-ops.mk diff | blob | history
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