fb86423733f190d888c233f59ac5aba8ea1d4e50
[openwrt/staging/thess.git] /
1 From 8e38e08f2c560328a873c35aff1a0dbea6a7d084 Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Tue, 1 Oct 2024 12:10:25 +0200
4 Subject: [PATCH 2/2] net: airoha: fix PSE memory configuration in
5 airoha_fe_pse_ports_init()
6
7 Align PSE memory configuration to vendor SDK. In particular, increase
8 initial value of PSE reserved memory in airoha_fe_pse_ports_init()
9 routine by the value used for the second Packet Processor Engine (PPE2)
10 and do not overwrite the default value.
11
12 Introduced by commit 23020f049327 ("net: airoha: Introduce ethernet support
13 for EN7581 SoC")
14
15 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
16 Reviewed-by: Simon Horman <horms@kernel.org>
17 Link: https://patch.msgid.link/20241001-airoha-eth-pse-fix-v2-2-9a56cdffd074@kernel.org
18 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
19 ---
20 drivers/net/ethernet/mediatek/airoha_eth.c | 6 ++++--
21 1 file changed, 4 insertions(+), 2 deletions(-)
22
23 --- a/drivers/net/ethernet/mediatek/airoha_eth.c
24 +++ b/drivers/net/ethernet/mediatek/airoha_eth.c
25 @@ -1166,11 +1166,13 @@ static void airoha_fe_pse_ports_init(str
26 [FE_PSE_PORT_GDM4] = 2,
27 [FE_PSE_PORT_CDM5] = 2,
28 };
29 + u32 all_rsv;
30 int q;
31
32 + all_rsv = airoha_fe_get_pse_all_rsv(eth);
33 /* hw misses PPE2 oq rsv */
34 - airoha_fe_set(eth, REG_FE_PSE_BUF_SET,
35 - PSE_RSV_PAGES * pse_port_num_queues[FE_PSE_PORT_PPE2]);
36 + all_rsv += PSE_RSV_PAGES * pse_port_num_queues[FE_PSE_PORT_PPE2];
37 + airoha_fe_set(eth, REG_FE_PSE_BUF_SET, all_rsv);
38
39 /* CMD1 */
40 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++)