git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From cd81d3a0695cc54ad6ac0ef4bbb67a7c8f55d592 Mon Sep 17 00:00:00 2001
   2 From: Niklas Cassel <cassel@kernel.org>
   3 Date: Thu, 2 May 2024 16:02:32 +0200
   4 Subject: [PATCH] arm64: dts: rockchip: add rk3588 pcie and php IOMMUs
   5
   6 The mmu600_pcie is connected with the five PCIe controllers.
   7 The mmu600_php is connected with the USB3 controller, the GMAC
   8 controllers, and the SATA controllers.
   9
  10 See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual).
  11
  12 The IOMMUs are disabled by default, as further patches are needed to
  13 program the SID/SSIDs in to the IOMMUs.
  14
  15 iommu: Default domain type: Translated
  16 iommu: DMA domain TLB invalidation policy: strict mode
  17 arm-smmu-v3 fc900000.iommu: ias 48-bit, oas 48-bit (features 0x001c1eaf)
  18 arm-smmu-v3 fc900000.iommu: allocated 65536 entries for cmdq
  19 arm-smmu-v3 fc900000.iommu: allocated 32768 entries for evtq
  20 arm-smmu-v3 fc900000.iommu: msi_domain absent - falling back to wired irqs
  21
  22 Additionally, the IOMMU correctly triggers an IOMMU fault when
  23 a PCIe device performs a write (since the device hasn't been
  24 assigned a SID/SSID):
  25 arm-smmu-v3 fc900000.iommu: event 0x02 received:
  26 arm-smmu-v3 fc900000.iommu:      0x0000010000000002
  27 arm-smmu-v3 fc900000.iommu:      0x0000000000000000
  28 arm-smmu-v3 fc900000.iommu:      0x0000000000000000
  29 arm-smmu-v3 fc900000.iommu:      0x0000000000000000
  30
  31 While this doesn't provide much value as is, having the devices as
  32 disabled in the device tree will allow developers to see that the rk3588
  33 actually has IOMMUs on the SoC.
  34
  35 Signed-off-by: Niklas Cassel <cassel@kernel.org>
  36 Link: https://lore.kernel.org/r/20240502140231.477049-2-cassel@kernel.org
  37 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  38 ---
  39  arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 24 +++++++++++++++++++++++
  40  1 file changed, 24 insertions(+)
  41
  42 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
  43 +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
  44 @@ -579,6 +579,30 @@
  45                 status = "disabled";
  46         };
  47
  48 +       mmu600_pcie: iommu@fc900000 {
  49 +               compatible = "arm,smmu-v3";
  50 +               reg = <0x0 0xfc900000 0x0 0x200000>;
  51 +               interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
  52 +                            <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
  53 +                            <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
  54 +                            <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
  55 +               interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
  56 +               #iommu-cells = <1>;
  57 +               status = "disabled";
  58 +       };
  59 +
  60 +       mmu600_php: iommu@fcb00000 {
  61 +               compatible = "arm,smmu-v3";
  62 +               reg = <0x0 0xfcb00000 0x0 0x200000>;
  63 +               interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
  64 +                            <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
  65 +                            <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
  66 +                            <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
  67 +               interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
  68 +               #iommu-cells = <1>;
  69 +               status = "disabled";
  70 +       };
  71 +
  72         pmu1grf: syscon@fd58a000 {
  73                 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
  74                 reg = <0x0 0xfd58a000 0x0 0x10000>;