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1 From b0f90a863ca5030fd074426b2b5095ef93f2c5bf Mon Sep 17 00:00:00 2001
2 From: "SkyLake.Huang" <skylake.huang@mediatek.com>
3 Date: Thu, 17 Oct 2024 11:22:12 +0800
4 Subject: [PATCH 2/3] net: phy: mediatek-ge-soc: Shrink line wrapping to 80
5 characters
6
7 This patch shrinks line wrapping to 80 chars. Also, in
8 tx_amp_fill_result(), use FIELD_PREP() to prettify code.
9
10 Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
11 Reviewed-by: Simon Horman <horms@kernel.org>
12 Signed-off-by: Andrew Lunn <andrew@lunn.ch>
13 ---
14 drivers/net/phy/mediatek-ge-soc.c | 125 +++++++++++++++++++++---------
15 1 file changed, 88 insertions(+), 37 deletions(-)
16
17 --- a/drivers/net/phy/mediatek-ge-soc.c
18 +++ b/drivers/net/phy/mediatek-ge-soc.c
19 @@ -342,7 +342,8 @@ static int cal_cycle(struct phy_device *
20 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
21 MTK_PHY_RG_AD_CAL_CLK, reg_val,
22 reg_val & MTK_PHY_DA_CAL_CLK, 500,
23 - ANALOG_INTERNAL_OPERATION_MAX_US, false);
24 + ANALOG_INTERNAL_OPERATION_MAX_US,
25 + false);
26 if (ret) {
27 phydev_err(phydev, "Calibration cycle timeout\n");
28 return ret;
29 @@ -441,40 +442,72 @@ static int tx_amp_fill_result(struct phy
30 }
31
32 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
33 - MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
34 + MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
35 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
36 + buf[0] + bias[0]));
37 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
38 - MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
39 + MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
40 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
41 + buf[0] + bias[1]));
42 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
43 - MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
44 + MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
45 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
46 + buf[0] + bias[2]));
47 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
48 - MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
49 + MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
50 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
51 + buf[0] + bias[3]));
52
53 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
54 - MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
55 + MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
56 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
57 + buf[1] + bias[4]));
58 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
59 - MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
60 + MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
61 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
62 + buf[1] + bias[5]));
63 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
64 - MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
65 + MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
66 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
67 + buf[1] + bias[6]));
68 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
69 - MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
70 + MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
71 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
72 + buf[1] + bias[7]));
73
74 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
75 - MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
76 + MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
77 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
78 + buf[2] + bias[8]));
79 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
80 - MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
81 + MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
82 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
83 + buf[2] + bias[9]));
84 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
85 - MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
86 + MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
87 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
88 + buf[2] + bias[10]));
89 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
90 - MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
91 + MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
92 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
93 + buf[2] + bias[11]));
94
95 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
96 - MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
97 + MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
98 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
99 + buf[3] + bias[12]));
100 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
101 - MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
102 + MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
103 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
104 + buf[3] + bias[13]));
105 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
106 - MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
107 + MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
108 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
109 + buf[3] + bias[14]));
110 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
111 - MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
112 + MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
113 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
114 + buf[3] + bias[15]));
115
116 return 0;
117 }
118 @@ -663,7 +696,8 @@ static int tx_vcm_cal_sw(struct phy_devi
119 goto restore;
120
121 /* We calibrate TX-VCM in different logic. Check upper index and then
122 - * lower index. If this calibration is valid, apply lower index's result.
123 + * lower index. If this calibration is valid, apply lower index's
124 + * result.
125 */
126 ret = upper_ret - lower_ret;
127 if (ret == 1) {
128 @@ -692,7 +726,8 @@ static int tx_vcm_cal_sw(struct phy_devi
129 } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
130 lower_ret == 0) {
131 ret = 0;
132 - phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
133 + phydev_warn(phydev,
134 + "TX-VCM SW cal result at high margin 0x%x\n",
135 upper_idx);
136 } else {
137 ret = -EINVAL;
138 @@ -796,7 +831,8 @@ static void mt7981_phy_finetune(struct p
139
140 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
141 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
142 - MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
143 + MTK_PHY_TR_OPEN_LOOP_EN_MASK |
144 + MTK_PHY_LPF_X_AVERAGE_MASK,
145 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
146
147 /* rg_tr_lpf_cnt_val = 512 */
148 @@ -865,7 +901,8 @@ static void mt7988_phy_finetune(struct p
149
150 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
151 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
152 - MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
153 + MTK_PHY_TR_OPEN_LOOP_EN_MASK |
154 + MTK_PHY_LPF_X_AVERAGE_MASK,
155 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
156
157 /* rg_tr_lpf_cnt_val = 1023 */
158 @@ -977,7 +1014,8 @@ static void mt798x_phy_eee(struct phy_de
159 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
160
161 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
162 - __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
163 + __phy_modify(phydev, MTK_PHY_LPI_REG_14,
164 + MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
165 FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
166
167 __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
168 @@ -987,7 +1025,8 @@ static void mt798x_phy_eee(struct phy_de
169 phy_modify_mmd(phydev, MDIO_MMD_VEND1,
170 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
171 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
172 - FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
173 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
174 + 0xff));
175 }
176
177 static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
178 @@ -1147,7 +1186,8 @@ static int mt798x_phy_hw_led_on_set(stru
179 (index ? 16 : 0), &priv->led_state);
180 if (changed)
181 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
182 - MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
183 + MTK_PHY_LED1_ON_CTRL :
184 + MTK_PHY_LED0_ON_CTRL,
185 MTK_PHY_LED_ON_MASK,
186 on ? MTK_PHY_LED_ON_FORCE_ON : 0);
187 else
188 @@ -1157,7 +1197,8 @@ static int mt798x_phy_hw_led_on_set(stru
189 static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
190 bool blinking)
191 {
192 - unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
193 + unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
194 + (index ? 16 : 0);
195 struct mtk_socphy_priv *priv = phydev->priv;
196 bool changed;
197
198 @@ -1170,8 +1211,10 @@ static int mt798x_phy_hw_led_blink_set(s
199 (index ? 16 : 0), &priv->led_state);
200 if (changed)
201 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
202 - MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL,
203 - blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
204 + MTK_PHY_LED1_BLINK_CTRL :
205 + MTK_PHY_LED0_BLINK_CTRL,
206 + blinking ?
207 + MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
208 else
209 return 0;
210 }
211 @@ -1237,7 +1280,8 @@ static int mt798x_phy_led_hw_is_supporte
212 static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
213 unsigned long *rules)
214 {
215 - unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
216 + unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
217 + (index ? 16 : 0);
218 unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
219 unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
220 struct mtk_socphy_priv *priv = phydev->priv;
221 @@ -1258,8 +1302,8 @@ static int mt798x_phy_led_hw_control_get
222 if (blink < 0)
223 return -EIO;
224
225 - if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX |
226 - MTK_PHY_LED_ON_LINKDOWN)) ||
227 + if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX |
228 + MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
229 (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX)))
230 set_bit(bit_netdev, &priv->led_state);
231 else
232 @@ -1333,17 +1377,23 @@ static int mt798x_phy_led_hw_control_set
233
234 if (rules & BIT(TRIGGER_NETDEV_RX)) {
235 blink |= (on & MTK_PHY_LED_ON_LINK) ?
236 - (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10RX : 0) |
237 - ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100RX : 0) |
238 - ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000RX : 0)) :
239 + (((on & MTK_PHY_LED_ON_LINK10) ?
240 + MTK_PHY_LED_BLINK_10RX : 0) |
241 + ((on & MTK_PHY_LED_ON_LINK100) ?
242 + MTK_PHY_LED_BLINK_100RX : 0) |
243 + ((on & MTK_PHY_LED_ON_LINK1000) ?
244 + MTK_PHY_LED_BLINK_1000RX : 0)) :
245 MTK_PHY_LED_BLINK_RX;
246 }
247
248 if (rules & BIT(TRIGGER_NETDEV_TX)) {
249 blink |= (on & MTK_PHY_LED_ON_LINK) ?
250 - (((on & MTK_PHY_LED_ON_LINK10) ? MTK_PHY_LED_BLINK_10TX : 0) |
251 - ((on & MTK_PHY_LED_ON_LINK100) ? MTK_PHY_LED_BLINK_100TX : 0) |
252 - ((on & MTK_PHY_LED_ON_LINK1000) ? MTK_PHY_LED_BLINK_1000TX : 0)) :
253 + (((on & MTK_PHY_LED_ON_LINK10) ?
254 + MTK_PHY_LED_BLINK_10TX : 0) |
255 + ((on & MTK_PHY_LED_ON_LINK100) ?
256 + MTK_PHY_LED_BLINK_100TX : 0) |
257 + ((on & MTK_PHY_LED_ON_LINK1000) ?
258 + MTK_PHY_LED_BLINK_1000TX : 0)) :
259 MTK_PHY_LED_BLINK_TX;
260 }
261
262 @@ -1400,7 +1450,8 @@ static int mt7988_phy_fix_leds_polaritie
263 /* Only now setup pinctrl to avoid bogus blinking */
264 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
265 if (IS_ERR(pinctrl))
266 - dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n");
267 + dev_err(&phydev->mdio.bus->dev,
268 + "Failed to setup PHY LED pinctrl\n");
269
270 return 0;
271 }
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