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1 From 3ffeb17a9a27a668efb6fbd074835e187910a9bb Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Fri, 7 Nov 2025 00:57:08 +0100
4 Subject: [PATCH 5/5] pinctrl: airoha: add support for Airoha AN7583 PINs
5
6 Add all the required entry to add suppot for Airoha AN7583 PINs.
7
8 Where possible the same function group are used from Airoha EN7581 to
9 reduce code duplication.
10
11 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
12 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
13 ---
14 drivers/pinctrl/mediatek/pinctrl-airoha.c | 747 +++++++++++++++++++++-
15 1 file changed, 740 insertions(+), 7 deletions(-)
16
17 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
18 +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
19 @@ -75,6 +75,7 @@
20 #define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20)
21 #define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19)
22 #define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18)
23 +#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18)
24 #define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17)
25 #define GPIO_PCM_SPI_MODE_MASK BIT(16)
26 #define GPIO_PCM2_MODE_MASK BIT(13)
27 @@ -132,6 +133,8 @@
28
29 /* CONF */
30 #define REG_I2C_SDA_E2 0x001c
31 +#define AN7583_I2C1_SCL_E2_MASK BIT(16)
32 +#define AN7583_I2C1_SDA_E2_MASK BIT(15)
33 #define SPI_MISO_E2_MASK BIT(14)
34 #define SPI_MOSI_E2_MASK BIT(13)
35 #define SPI_CLK_E2_MASK BIT(12)
36 @@ -139,12 +142,16 @@
37 #define PCIE2_RESET_E2_MASK BIT(10)
38 #define PCIE1_RESET_E2_MASK BIT(9)
39 #define PCIE0_RESET_E2_MASK BIT(8)
40 +#define AN7583_MDIO_0_E2_MASK BIT(5)
41 +#define AN7583_MDC_0_E2_MASK BIT(4)
42 #define UART1_RXD_E2_MASK BIT(3)
43 #define UART1_TXD_E2_MASK BIT(2)
44 #define I2C_SCL_E2_MASK BIT(1)
45 #define I2C_SDA_E2_MASK BIT(0)
46
47 #define REG_I2C_SDA_E4 0x0020
48 +#define AN7583_I2C1_SCL_E4_MASK BIT(16)
49 +#define AN7583_I2C1_SDA_E4_MASK BIT(15)
50 #define SPI_MISO_E4_MASK BIT(14)
51 #define SPI_MOSI_E4_MASK BIT(13)
52 #define SPI_CLK_E4_MASK BIT(12)
53 @@ -152,6 +159,8 @@
54 #define PCIE2_RESET_E4_MASK BIT(10)
55 #define PCIE1_RESET_E4_MASK BIT(9)
56 #define PCIE0_RESET_E4_MASK BIT(8)
57 +#define AN7583_MDIO_0_E4_MASK BIT(5)
58 +#define AN7583_MDC_0_E4_MASK BIT(4)
59 #define UART1_RXD_E4_MASK BIT(3)
60 #define UART1_TXD_E4_MASK BIT(2)
61 #define I2C_SCL_E4_MASK BIT(1)
62 @@ -163,6 +172,8 @@
63 #define REG_GPIO_H_E4 0x0030
64
65 #define REG_I2C_SDA_PU 0x0044
66 +#define AN7583_I2C1_SCL_PU_MASK BIT(16)
67 +#define AN7583_I2C1_SDA_PU_MASK BIT(15)
68 #define SPI_MISO_PU_MASK BIT(14)
69 #define SPI_MOSI_PU_MASK BIT(13)
70 #define SPI_CLK_PU_MASK BIT(12)
71 @@ -170,12 +181,16 @@
72 #define PCIE2_RESET_PU_MASK BIT(10)
73 #define PCIE1_RESET_PU_MASK BIT(9)
74 #define PCIE0_RESET_PU_MASK BIT(8)
75 +#define AN7583_MDIO_0_PU_MASK BIT(5)
76 +#define AN7583_MDC_0_PU_MASK BIT(4)
77 #define UART1_RXD_PU_MASK BIT(3)
78 #define UART1_TXD_PU_MASK BIT(2)
79 #define I2C_SCL_PU_MASK BIT(1)
80 #define I2C_SDA_PU_MASK BIT(0)
81
82 #define REG_I2C_SDA_PD 0x0048
83 +#define AN7583_I2C1_SDA_PD_MASK BIT(16)
84 +#define AN7583_I2C1_SCL_PD_MASK BIT(15)
85 #define SPI_MISO_PD_MASK BIT(14)
86 #define SPI_MOSI_PD_MASK BIT(13)
87 #define SPI_CLK_PD_MASK BIT(12)
88 @@ -183,6 +198,8 @@
89 #define PCIE2_RESET_PD_MASK BIT(10)
90 #define PCIE1_RESET_PD_MASK BIT(9)
91 #define PCIE0_RESET_PD_MASK BIT(8)
92 +#define AN7583_MDIO_0_PD_MASK BIT(5)
93 +#define AN7583_MDC_0_PD_MASK BIT(4)
94 #define UART1_RXD_PD_MASK BIT(3)
95 #define UART1_TXD_PD_MASK BIT(2)
96 #define I2C_SCL_PD_MASK BIT(1)
97 @@ -630,10 +647,223 @@ static const struct pingroup en7581_pinc
98 PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
99 };
100
101 +static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
102 + PINCTRL_PIN(2, "gpio0"),
103 + PINCTRL_PIN(3, "gpio1"),
104 + PINCTRL_PIN(4, "gpio2"),
105 + PINCTRL_PIN(5, "gpio3"),
106 + PINCTRL_PIN(6, "gpio4"),
107 + PINCTRL_PIN(7, "gpio5"),
108 + PINCTRL_PIN(8, "gpio6"),
109 + PINCTRL_PIN(9, "gpio7"),
110 + PINCTRL_PIN(10, "gpio8"),
111 + PINCTRL_PIN(11, "gpio9"),
112 + PINCTRL_PIN(12, "gpio10"),
113 + PINCTRL_PIN(13, "gpio11"),
114 + PINCTRL_PIN(14, "gpio12"),
115 + PINCTRL_PIN(15, "gpio13"),
116 + PINCTRL_PIN(16, "gpio14"),
117 + PINCTRL_PIN(17, "gpio15"),
118 + PINCTRL_PIN(18, "gpio16"),
119 + PINCTRL_PIN(19, "gpio17"),
120 + PINCTRL_PIN(20, "gpio18"),
121 + PINCTRL_PIN(21, "gpio19"),
122 + PINCTRL_PIN(22, "gpio20"),
123 + PINCTRL_PIN(23, "gpio21"),
124 + PINCTRL_PIN(24, "gpio22"),
125 + PINCTRL_PIN(25, "gpio23"),
126 + PINCTRL_PIN(26, "gpio24"),
127 + PINCTRL_PIN(27, "gpio25"),
128 + PINCTRL_PIN(28, "gpio26"),
129 + PINCTRL_PIN(29, "gpio27"),
130 + PINCTRL_PIN(30, "gpio28"),
131 + PINCTRL_PIN(31, "gpio29"),
132 + PINCTRL_PIN(32, "gpio30"),
133 + PINCTRL_PIN(33, "gpio31"),
134 + PINCTRL_PIN(34, "gpio32"),
135 + PINCTRL_PIN(35, "gpio33"),
136 + PINCTRL_PIN(36, "gpio34"),
137 + PINCTRL_PIN(37, "gpio35"),
138 + PINCTRL_PIN(38, "gpio36"),
139 + PINCTRL_PIN(39, "gpio37"),
140 + PINCTRL_PIN(40, "gpio38"),
141 + PINCTRL_PIN(41, "i2c0_scl"),
142 + PINCTRL_PIN(42, "i2c0_sda"),
143 + PINCTRL_PIN(43, "i2c1_scl"),
144 + PINCTRL_PIN(44, "i2c1_sda"),
145 + PINCTRL_PIN(45, "spi_clk"),
146 + PINCTRL_PIN(46, "spi_cs"),
147 + PINCTRL_PIN(47, "spi_mosi"),
148 + PINCTRL_PIN(48, "spi_miso"),
149 + PINCTRL_PIN(49, "uart_txd"),
150 + PINCTRL_PIN(50, "uart_rxd"),
151 + PINCTRL_PIN(51, "pcie_reset0"),
152 + PINCTRL_PIN(52, "pcie_reset1"),
153 + PINCTRL_PIN(53, "mdc_0"),
154 + PINCTRL_PIN(54, "mdio_0"),
155 +};
156 +
157 +static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
158 +static const int an7583_pon_tod_1pps_pins[] = { 32 };
159 +static const int an7583_gsw_tod_1pps_pins[] = { 32 };
160 +static const int an7583_sipo_pins[] = { 34, 35 };
161 +static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
162 +static const int an7583_mdio_pins[] = { 43, 44 };
163 +static const int an7583_uart2_pins[] = { 34, 35 };
164 +static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
165 +static const int an7583_hsuart_pins[] = { 30, 31 };
166 +static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
167 +static const int an7583_npu_uart_pins[] = { 7, 8 };
168 +static const int an7583_uart4_pins[] = { 7, 8 };
169 +static const int an7583_uart5_pins[] = { 23, 24 };
170 +static const int an7583_i2c0_pins[] = { 41, 42 };
171 +static const int an7583_i2c1_pins[] = { 43, 44 };
172 +static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
173 +static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
174 +static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
175 +static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
176 +static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
177 +static const int an7583_spi_quad_pins[] = { 25, 26 };
178 +static const int an7583_spi_cs1_pins[] = { 27 };
179 +static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
180 +static const int an7583_pcm_spi_rst_pins[] = { 14 };
181 +static const int an7583_pcm_spi_cs1_pins[] = { 24 };
182 +static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
183 +static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
184 +static const int an7583_gpio0_pins[] = { 2 };
185 +static const int an7583_gpio1_pins[] = { 3 };
186 +static const int an7583_gpio2_pins[] = { 4 };
187 +static const int an7583_gpio3_pins[] = { 5 };
188 +static const int an7583_gpio4_pins[] = { 6 };
189 +static const int an7583_gpio5_pins[] = { 7 };
190 +static const int an7583_gpio6_pins[] = { 8 };
191 +static const int an7583_gpio7_pins[] = { 9 };
192 +static const int an7583_gpio8_pins[] = { 10 };
193 +static const int an7583_gpio9_pins[] = { 11 };
194 +static const int an7583_gpio10_pins[] = { 12 };
195 +static const int an7583_gpio11_pins[] = { 13 };
196 +static const int an7583_gpio12_pins[] = { 14 };
197 +static const int an7583_gpio13_pins[] = { 15 };
198 +static const int an7583_gpio14_pins[] = { 16 };
199 +static const int an7583_gpio15_pins[] = { 17 };
200 +static const int an7583_gpio16_pins[] = { 18 };
201 +static const int an7583_gpio17_pins[] = { 19 };
202 +static const int an7583_gpio18_pins[] = { 20 };
203 +static const int an7583_gpio19_pins[] = { 21 };
204 +static const int an7583_gpio20_pins[] = { 22 };
205 +static const int an7583_gpio21_pins[] = { 24 };
206 +static const int an7583_gpio23_pins[] = { 25 };
207 +static const int an7583_gpio24_pins[] = { 26 };
208 +static const int an7583_gpio25_pins[] = { 27 };
209 +static const int an7583_gpio26_pins[] = { 28 };
210 +static const int an7583_gpio27_pins[] = { 29 };
211 +static const int an7583_gpio28_pins[] = { 30 };
212 +static const int an7583_gpio29_pins[] = { 31 };
213 +static const int an7583_gpio30_pins[] = { 32 };
214 +static const int an7583_gpio31_pins[] = { 33 };
215 +static const int an7583_gpio33_pins[] = { 35 };
216 +static const int an7583_gpio34_pins[] = { 36 };
217 +static const int an7583_gpio35_pins[] = { 37 };
218 +static const int an7583_gpio36_pins[] = { 38 };
219 +static const int an7583_gpio37_pins[] = { 39 };
220 +static const int an7583_gpio38_pins[] = { 40 };
221 +static const int an7583_gpio39_pins[] = { 41 };
222 +static const int an7583_gpio40_pins[] = { 42 };
223 +static const int an7583_gpio41_pins[] = { 43 };
224 +static const int an7583_gpio42_pins[] = { 44 };
225 +static const int an7583_gpio43_pins[] = { 45 };
226 +static const int an7583_gpio44_pins[] = { 46 };
227 +static const int an7583_gpio45_pins[] = { 47 };
228 +static const int an7583_gpio46_pins[] = { 48 };
229 +static const int an7583_gpio47_pins[] = { 49 };
230 +static const int an7583_gpio48_pins[] = { 50 };
231 +static const int an7583_pcie_reset0_pins[] = { 51 };
232 +static const int an7583_pcie_reset1_pins[] = { 52 };
233 +
234 +static const struct pingroup an7583_pinctrl_groups[] = {
235 + PINCTRL_PIN_GROUP("pon", an7583_pon),
236 + PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
237 + PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
238 + PINCTRL_PIN_GROUP("sipo", an7583_sipo),
239 + PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
240 + PINCTRL_PIN_GROUP("mdio", an7583_mdio),
241 + PINCTRL_PIN_GROUP("uart2", an7583_uart2),
242 + PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
243 + PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
244 + PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
245 + PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
246 + PINCTRL_PIN_GROUP("uart4", an7583_uart4),
247 + PINCTRL_PIN_GROUP("uart5", an7583_uart5),
248 + PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
249 + PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
250 + PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
251 + PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
252 + PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
253 + PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
254 + PINCTRL_PIN_GROUP("spi", an7583_spi),
255 + PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
256 + PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
257 + PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
258 + PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
259 + PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
260 + PINCTRL_PIN_GROUP("emmc", an7583_emmc),
261 + PINCTRL_PIN_GROUP("pnand", an7583_pnand),
262 + PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
263 + PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
264 + PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
265 + PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
266 + PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
267 + PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
268 + PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
269 + PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
270 + PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
271 + PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
272 + PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
273 + PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
274 + PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
275 + PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
276 + PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
277 + PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
278 + PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
279 + PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
280 + PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
281 + PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
282 + PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
283 + PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
284 + PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
285 + PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
286 + PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
287 + PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
288 + PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
289 + PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
290 + PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
291 + PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
292 + PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
293 + PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
294 + PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
295 + PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
296 + PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
297 + PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
298 + PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
299 + PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
300 + PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
301 + PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
302 + PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
303 + PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
304 + PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
305 + PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
306 + PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
307 + PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
308 + PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
309 + PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
310 + PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
311 +};
312 +
313 static const char *const pon_groups[] = { "pon" };
314 static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
315 static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
316 static const char *const mdio_groups[] = { "mdio" };
317 +static const char *const an7583_mdio_groups[] = { "mdio" };
318 static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
319 "hsuart_cts_rts", "uart4",
320 "uart5" };
321 @@ -646,11 +876,16 @@ static const char *const pcm_spi_groups[
322 "pcm_spi_cs2_p156",
323 "pcm_spi_cs2_p128",
324 "pcm_spi_cs3", "pcm_spi_cs4" };
325 +static const char *const an7583_pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
326 + "pcm_spi_rst", "pcm_spi_cs1",
327 + "pcm_spi_cs2", "pcm_spi_cs3",
328 + "pcm_spi_cs4" };
329 static const char *const i2s_groups[] = { "i2s" };
330 static const char *const emmc_groups[] = { "emmc" };
331 static const char *const pnand_groups[] = { "pnand" };
332 static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
333 "pcie_reset2" };
334 +static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
335 static const char *const pwm_groups[] = { "gpio0", "gpio1",
336 "gpio2", "gpio3",
337 "gpio4", "gpio5",
338 @@ -689,6 +924,22 @@ static const char *const phy3_led1_group
339 "gpio45", "gpio46" };
340 static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
341 "gpio45", "gpio46" };
342 +static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
343 + "gpio3", "gpio4" };
344 +static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
345 + "gpio3", "gpio4" };
346 +static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
347 + "gpio3", "gpio4" };
348 +static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
349 + "gpio3", "gpio4" };
350 +static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
351 + "gpio10", "gpio11" };
352 +static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
353 + "gpio10", "gpio11" };
354 +static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
355 + "gpio10", "gpio11" };
356 +static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
357 + "gpio10", "gpio11" };
358
359 static const struct airoha_pinctrl_func_group pon_func_group[] = {
360 {
361 @@ -766,6 +1017,25 @@ static const struct airoha_pinctrl_func_
362 },
363 };
364
365 +static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
366 + {
367 + .name = "mdio",
368 + .regmap[0] = {
369 + AIROHA_FUNC_MUX,
370 + REG_GPIO_PON_MODE,
371 + GPIO_SGMII_MDIO_MODE_MASK,
372 + GPIO_SGMII_MDIO_MODE_MASK
373 + },
374 + .regmap[1] = {
375 + AIROHA_FUNC_MUX,
376 + REG_GPIO_SPI_CS1_MODE,
377 + GPIO_MDC_IO_MASTER_MODE_MODE,
378 + GPIO_MDC_IO_MASTER_MODE_MODE
379 + },
380 + .regmap_size = 2,
381 + },
382 +};
383 +
384 static const struct airoha_pinctrl_func_group uart_func_group[] = {
385 {
386 .name = "uart2",
387 @@ -1007,6 +1277,73 @@ static const struct airoha_pinctrl_func_
388 },
389 };
390
391 +static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
392 + {
393 + .name = "pcm_spi",
394 + .regmap[0] = {
395 + AIROHA_FUNC_MUX,
396 + REG_GPIO_SPI_CS1_MODE,
397 + GPIO_PCM_SPI_MODE_MASK,
398 + GPIO_PCM_SPI_MODE_MASK
399 + },
400 + .regmap_size = 1,
401 + }, {
402 + .name = "pcm_spi_int",
403 + .regmap[0] = {
404 + AIROHA_FUNC_MUX,
405 + REG_GPIO_SPI_CS1_MODE,
406 + GPIO_PCM_INT_MODE_MASK,
407 + GPIO_PCM_INT_MODE_MASK
408 + },
409 + .regmap_size = 1,
410 + }, {
411 + .name = "pcm_spi_rst",
412 + .regmap[0] = {
413 + AIROHA_FUNC_MUX,
414 + REG_GPIO_SPI_CS1_MODE,
415 + GPIO_PCM_RESET_MODE_MASK,
416 + GPIO_PCM_RESET_MODE_MASK
417 + },
418 + .regmap_size = 1,
419 + }, {
420 + .name = "pcm_spi_cs1",
421 + .regmap[0] = {
422 + AIROHA_FUNC_MUX,
423 + REG_GPIO_SPI_CS1_MODE,
424 + GPIO_PCM_SPI_CS1_MODE_MASK,
425 + GPIO_PCM_SPI_CS1_MODE_MASK
426 + },
427 + .regmap_size = 1,
428 + }, {
429 + .name = "pcm_spi_cs2",
430 + .regmap[0] = {
431 + AIROHA_FUNC_MUX,
432 + REG_GPIO_SPI_CS1_MODE,
433 + AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
434 + AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
435 + },
436 + .regmap_size = 1,
437 + }, {
438 + .name = "pcm_spi_cs3",
439 + .regmap[0] = {
440 + AIROHA_FUNC_MUX,
441 + REG_GPIO_SPI_CS1_MODE,
442 + GPIO_PCM_SPI_CS3_MODE_MASK,
443 + GPIO_PCM_SPI_CS3_MODE_MASK
444 + },
445 + .regmap_size = 1,
446 + }, {
447 + .name = "pcm_spi_cs4",
448 + .regmap[0] = {
449 + AIROHA_FUNC_MUX,
450 + REG_GPIO_SPI_CS1_MODE,
451 + GPIO_PCM_SPI_CS4_MODE_MASK,
452 + GPIO_PCM_SPI_CS4_MODE_MASK
453 + },
454 + .regmap_size = 1,
455 + },
456 +};
457 +
458 static const struct airoha_pinctrl_func_group i2s_func_group[] = {
459 {
460 .name = "i2s",
461 @@ -1077,6 +1414,28 @@ static const struct airoha_pinctrl_func_
462 },
463 };
464
465 +static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
466 + {
467 + .name = "pcie_reset0",
468 + .regmap[0] = {
469 + AIROHA_FUNC_MUX,
470 + REG_GPIO_PON_MODE,
471 + GPIO_PCIE_RESET0_MASK,
472 + GPIO_PCIE_RESET0_MASK
473 + },
474 + .regmap_size = 1,
475 + }, {
476 + .name = "pcie_reset1",
477 + .regmap[0] = {
478 + AIROHA_FUNC_MUX,
479 + REG_GPIO_PON_MODE,
480 + GPIO_PCIE_RESET1_MASK,
481 + GPIO_PCIE_RESET1_MASK
482 + },
483 + .regmap_size = 1,
484 + },
485 +};
486 +
487 /* PWM */
488 #define AIROHA_PINCTRL_PWM(gpio, mux_val) \
489 { \
490 @@ -1273,6 +1632,94 @@ static const struct airoha_pinctrl_func_
491 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
492 };
493
494 +static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
495 + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
496 + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
497 + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
498 + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
499 + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
500 + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
501 + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
502 + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
503 +};
504 +
505 +static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
506 + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
507 + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
508 + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
509 + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
510 + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
511 + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
512 + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
513 + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
514 +};
515 +
516 +static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
517 + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
518 + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
519 + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
520 + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
521 + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
522 + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
523 + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
524 + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
525 +};
526 +
527 +static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
528 + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
529 + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
530 + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
531 + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
532 + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
533 + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
534 + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
535 + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
536 +};
537 +
538 +static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
539 + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
540 + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
541 + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
542 + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
543 + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
544 + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
545 + AIROHA_PINCTRL_PHY_LED1("gpio1", GPIO_LAN3_LED1_MODE_MASK,
546 + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
547 +};
548 +
549 +static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
550 + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
551 + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
552 + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
553 + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
554 + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
555 + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
556 + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
557 + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
558 +};
559 +
560 +static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
561 + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
562 + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
563 + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
564 + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
565 + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
566 + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
567 + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
568 + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
569 +};
570 +
571 +static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
572 + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
573 + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
574 + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
575 + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
576 + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
577 + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
578 + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
579 + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
580 +};
581 +
582 static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
583 PINCTRL_FUNC_DESC("pon", pon),
584 PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
585 @@ -1299,6 +1746,31 @@ static const struct airoha_pinctrl_func
586 PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
587 };
588
589 +static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
590 + PINCTRL_FUNC_DESC("pon", pon),
591 + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
592 + PINCTRL_FUNC_DESC("sipo", sipo),
593 + PINCTRL_FUNC_DESC("mdio", an7583_mdio),
594 + PINCTRL_FUNC_DESC("uart", uart),
595 + PINCTRL_FUNC_DESC("i2c", i2c),
596 + PINCTRL_FUNC_DESC("jtag", jtag),
597 + PINCTRL_FUNC_DESC("pcm", pcm),
598 + PINCTRL_FUNC_DESC("spi", spi),
599 + PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
600 + PINCTRL_FUNC_DESC("emmc", emmc),
601 + PINCTRL_FUNC_DESC("pnand", pnand),
602 + PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
603 + PINCTRL_FUNC_DESC("pwm", pwm),
604 + PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
605 + PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
606 + PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
607 + PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
608 + PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
609 + PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
610 + PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
611 + PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
612 +};
613 +
614 static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
615 PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
616 PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
617 @@ -1360,6 +1832,62 @@ static const struct airoha_pinctrl_conf
618 PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
619 };
620
621 +static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
622 + PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
623 + PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
624 + PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
625 + PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
626 + PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
627 + PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
628 + PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
629 + PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
630 + PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
631 + PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
632 + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
633 + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
634 + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
635 + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
636 + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
637 + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
638 + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
639 + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
640 + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
641 + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)),
642 + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
643 + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
644 + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
645 + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
646 + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
647 + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
648 + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
649 + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
650 + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
651 + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
652 + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
653 + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
654 + PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
655 + PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
656 + PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
657 + PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
658 + PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
659 + PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
660 + PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
661 + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
662 + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
663 + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
664 + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
665 + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
666 + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
667 + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
668 + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
669 + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
670 + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
671 + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
672 + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
673 + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
674 + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
675 +};
676 +
677 static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
678 PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
679 PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
680 @@ -1421,6 +1949,62 @@ static const struct airoha_pinctrl_conf
681 PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
682 };
683
684 +static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
685 + PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
686 + PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
687 + PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
688 + PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
689 + PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
690 + PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
691 + PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
692 + PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
693 + PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
694 + PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
695 + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
696 + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
697 + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
698 + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
699 + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
700 + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
701 + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
702 + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
703 + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
704 + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)),
705 + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
706 + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
707 + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
708 + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
709 + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
710 + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
711 + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
712 + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
713 + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
714 + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
715 + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
716 + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
717 + PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
718 + PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
719 + PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
720 + PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
721 + PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
722 + PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
723 + PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
724 + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
725 + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
726 + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
727 + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
728 + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
729 + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
730 + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
731 + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
732 + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
733 + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
734 + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
735 + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
736 + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
737 + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
738 +};
739 +
740 static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
741 PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
742 PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
743 @@ -1482,6 +2066,62 @@ static const struct airoha_pinctrl_conf
744 PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
745 };
746
747 +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
748 + PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
749 + PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
750 + PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
751 + PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
752 + PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
753 + PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
754 + PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
755 + PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
756 + PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
757 + PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
758 + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
759 + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
760 + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
761 + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
762 + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
763 + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
764 + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
765 + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
766 + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
767 + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)),
768 + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
769 + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
770 + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
771 + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
772 + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
773 + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
774 + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
775 + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
776 + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
777 + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
778 + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
779 + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
780 + PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
781 + PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
782 + PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
783 + PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
784 + PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
785 + PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
786 + PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
787 + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
788 + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
789 + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
790 + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
791 + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
792 + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
793 + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
794 + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
795 + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
796 + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
797 + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
798 + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
799 + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
800 + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
801 +};
802 +
803 static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
804 PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
805 PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
806 @@ -1543,12 +2183,73 @@ static const struct airoha_pinctrl_conf
807 PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
808 };
809
810 +static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
811 + PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
812 + PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
813 + PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
814 + PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
815 + PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
816 + PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
817 + PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
818 + PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
819 + PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
820 + PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
821 + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
822 + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
823 + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
824 + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
825 + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
826 + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
827 + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
828 + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
829 + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
830 + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)),
831 + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
832 + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
833 + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
834 + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
835 + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
836 + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
837 + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
838 + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
839 + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
840 + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
841 + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
842 + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
843 + PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
844 + PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
845 + PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
846 + PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
847 + PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
848 + PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
849 + PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
850 + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
851 + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
852 + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
853 + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
854 + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
855 + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
856 + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
857 + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
858 + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
859 + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
860 + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
861 + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
862 + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
863 + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
864 +};
865 +
866 static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
867 PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
868 PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
869 PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
870 };
871
872 +static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
873 + PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
874 + PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
875 +};
876 +
877 static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
878 struct pinctrl_gpio_range *range,
879 int pin)
880 @@ -1714,7 +2415,7 @@ static const struct irq_chip airoha_gpio
881 };
882
883 static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
884 - struct platform_device *pdev)
885 + struct platform_device *pdev)
886 {
887 struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
888 struct gpio_chip *gc = &chip->chip;
889 @@ -1749,7 +2450,7 @@ static int airoha_pinctrl_add_gpiochip(s
890 return irq;
891
892 err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED,
893 - dev_name(dev), pinctrl);
894 + dev_name(dev), pinctrl);
895 if (err) {
896 dev_err(dev, "error requesting irq %d: %d\n", irq, err);
897 return err;
898 @@ -1813,8 +2514,8 @@ static int airoha_pinmux_set_mux(struct
899 }
900
901 static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev,
902 - struct pinctrl_gpio_range *range,
903 - unsigned int p, bool input)
904 + struct pinctrl_gpio_range *range,
905 + unsigned int p, bool input)
906 {
907 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
908 u32 mask, index;
909 @@ -1904,7 +2605,7 @@ static int airoha_pinctrl_set_conf(struc
910
911
912 if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask,
913 - val << __ffs(reg->mask)))
914 + val << __ffs(reg->mask)))
915 return -EINVAL;
916
917 return 0;
918 @@ -2123,8 +2824,8 @@ static int airoha_pinconf_group_get(stru
919
920 for (i = 0; i < pinctrl->grps[group].npins; i++) {
921 if (airoha_pinconf_get(pctrl_dev,
922 - pinctrl->grps[group].pins[i],
923 - config))
924 + pinctrl->grps[group].pins[i],
925 + config))
926 return -ENOTSUPP;
927
928 if (i && cur_config != *config)
929 @@ -2285,8 +2986,40 @@ static const struct airoha_pinctrl_match
930 },
931 };
932
933 +static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
934 + .pins = an7583_pinctrl_pins,
935 + .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
936 + .grps = an7583_pinctrl_groups,
937 + .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
938 + .funcs = an7583_pinctrl_funcs,
939 + .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
940 + .confs_info = {
941 + [AIROHA_PINCTRL_CONFS_PULLUP] = {
942 + .confs = an7583_pinctrl_pullup_conf,
943 + .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
944 + },
945 + [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
946 + .confs = an7583_pinctrl_pulldown_conf,
947 + .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
948 + },
949 + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
950 + .confs = en7581_pinctrl_drive_e2_conf,
951 + .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
952 + },
953 + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
954 + .confs = an7583_pinctrl_drive_e4_conf,
955 + .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
956 + },
957 + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
958 + .confs = an7583_pinctrl_pcie_rst_od_conf,
959 + .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
960 + },
961 + },
962 +};
963 +
964 static const struct of_device_id airoha_pinctrl_of_match[] = {
965 { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
966 + { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
967 { /* sentinel */ }
968 };
969 MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
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