git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From bbd3778da16b3d448832b843f80bcde1aff26290 Mon Sep 17 00:00:00 2001
   2 From: Sebastian Reichel <sebastian.reichel@collabora.com>
   3 Date: Fri, 20 Oct 2023 16:11:42 +0200
   4 Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add USB3 host controller
   5
   6 RK3588 has three USB3 controllers. This adds the host-only controller,
   7 which is using the naneng-combphy shared with PCIe and SATA.
   8
   9 The other two are dual-role and using a different PHY that is not yet
  10 supported upstream.
  11
  12 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  13 Link: https://lore.kernel.org/r/20231020150022.48725-4-sebastian.reichel@collabora.com
  14 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  15 ---
  16  arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++
  17  1 file changed, 21 insertions(+)
  18
  19 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
  20 +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
  21 @@ -443,6 +443,27 @@
  22                 status = "disabled";
  23         };
  24
  25 +       usb_host2_xhci: usb@fcd00000 {
  26 +               compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
  27 +               reg = <0x0 0xfcd00000 0x0 0x400000>;
  28 +               interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
  29 +               clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
  30 +                        <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
  31 +                        <&cru CLK_PIPEPHY2_PIPE_U3_G>;
  32 +               clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
  33 +               dr_mode = "host";
  34 +               phys = <&combphy2_psu PHY_TYPE_USB3>;
  35 +               phy-names = "usb3-phy";
  36 +               phy_type = "utmi_wide";
  37 +               resets = <&cru SRST_A_USB3OTG2>;
  38 +               snps,dis_enblslpm_quirk;
  39 +               snps,dis-u2-freeclk-exists-quirk;
  40 +               snps,dis-del-phy-power-chg-quirk;
  41 +               snps,dis-tx-ipgap-linecheck-quirk;
  42 +               snps,dis_rxdet_inp3_quirk;
  43 +               status = "disabled";
  44 +       };
  45 +
  46         pmu1grf: syscon@fd58a000 {
  47                 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
  48                 reg = <0x0 0xfd58a000 0x0 0x10000>;