git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From b2e668a60ed866ba960acb5310d1fb6bf81d154f Mon Sep 17 00:00:00 2001
   2 From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
   3 Date: Sun, 23 Feb 2025 11:31:40 +0200
   4 Subject: arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on
   5  RK3588
   6
   7 VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
   8 more accurate pixel clock source to improve handling of display modes up
   9 to 4K@60Hz on video ports 0, 1 and 2.
  10
  11 The HDMI1 PHY PLL clock source cannot be added directly to vop node in
  12 rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an
  13 optional feature and its PHY node belongs to a separate (extra) DT file.
  14
  15 Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its
  16 clocks & clock-names properties in the extra DT file.
  17
  18 Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
  19 Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com
  20 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  21
  22 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
  23 +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
  24 @@ -509,3 +509,24 @@
  25                 status = "disabled";
  26         };
  27  };
  28 +
  29 +&vop {
  30 +       clocks = <&cru ACLK_VOP>,
  31 +                <&cru HCLK_VOP>,
  32 +                <&cru DCLK_VOP0>,
  33 +                <&cru DCLK_VOP1>,
  34 +                <&cru DCLK_VOP2>,
  35 +                <&cru DCLK_VOP3>,
  36 +                <&cru PCLK_VOP_ROOT>,
  37 +                <&hdptxphy0>,
  38 +                <&hdptxphy1>;
  39 +       clock-names = "aclk",
  40 +                     "hclk",
  41 +                     "dclk_vp0",
  42 +                     "dclk_vp1",
  43 +                     "dclk_vp2",
  44 +                     "dclk_vp3",
  45 +                     "pclk_vop",
  46 +                     "pll_hdmiphy0",
  47 +                     "pll_hdmiphy1";
  48 +};