git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From 61bcabdb69418215ea05bdc48cb88459d757f505 Mon Sep 17 00:00:00 2001
   2 From: "SkyLake.Huang" <skylake.huang@mediatek.com>
   3 Date: Fri, 4 Oct 2024 18:24:06 +0800
   4 Subject: [PATCH 2/9] net: phy: mediatek: Fix spelling errors and rearrange
   5  variables
   6
   7 This patch fixes spelling errors which comes from mediatek-ge-soc.c and
   8 rearrange variables with reverse Xmas tree order.
   9
  10 Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
  11 ---
  12  drivers/net/phy/mediatek/mtk-ge-soc.c | 19 ++++++++++---------
  13  1 file changed, 10 insertions(+), 9 deletions(-)
  14
  15 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c
  16 +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
  17 @@ -408,16 +408,17 @@ static int tx_offset_cal_efuse(struct ph
  18
  19  static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
  20  {
  21 -       int i;
  22 -       int bias[16] = {};
  23 -       const int vals_9461[16] = { 7, 1, 4, 7,
  24 -                                   7, 1, 4, 7,
  25 -                                   7, 1, 4, 7,
  26 -                                   7, 1, 4, 7 };
  27         const int vals_9481[16] = { 10, 6, 6, 10,
  28                                     10, 6, 6, 10,
  29                                     10, 6, 6, 10,
  30                                     10, 6, 6, 10 };
  31 +       const int vals_9461[16] = { 7, 1, 4, 7,
  32 +                                   7, 1, 4, 7,
  33 +                                   7, 1, 4, 7,
  34 +                                   7, 1, 4, 7 };
  35 +       int bias[16] = {};
  36 +       int i;
  37 +
  38         switch (phydev->drv->phy_id) {
  39         case MTK_GPHY_ID_MT7981:
  40                 /* We add some calibration to efuse values
  41 @@ -1069,10 +1070,10 @@ static int start_cal(struct phy_device *
  42
  43  static int mt798x_phy_calibration(struct phy_device *phydev)
  44  {
  45 +       struct nvmem_cell *cell;
  46         int ret = 0;
  47 -       u32 *buf;
  48         size_t len;
  49 -       struct nvmem_cell *cell;
  50 +       u32 *buf;
  51
  52         cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
  53         if (IS_ERR(cell)) {
  54 @@ -1415,7 +1416,7 @@ static int mt7988_phy_probe_shared(struc
  55          * LED_C and LED_D respectively. At the same time those pins are used to
  56          * bootstrap configuration of the reference clock source (LED_A),
  57          * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
  58 -        * In practise this is done using a LED and a resistor pulling the pin
  59 +        * In practice this is done using a LED and a resistor pulling the pin
  60          * either to GND or to VIO.
  61          * The detected value at boot time is accessible at run-time using the
  62          * TPBANK0 register located in the gpio base of the pinctrl, in order