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   1 From: Gabor Juhos <j4g8y7@gmail.com>
   2 Subject: [PATCH] clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure
   3 Date: Fri, 15 Mar 2024 17:16:41 +0100
   4
   5 Booting v6.8 results in a hang on various IPQ5018 based boards.
   6 Investigating the problem showed that the hang happens when the
   7 clk_alpha_pll_stromer_plus_set_rate() function tries to write
   8 into the PLL_MODE register of the APSS PLL.
   9
  10 Checking the downstream code revealed that it uses [1] stromer
  11 specific operations for IPQ5018, whereas in the current code
  12 the stromer plus specific operations are used.
  13
  14 The ops in the 'ipq_pll_stromer_plus' clock definition can't be
  15 changed since that is needed for IPQ5332, so add a new alpha pll
  16 clock declaration which uses the correct stromer ops and use this
  17 new clock for IPQ5018 to avoid the boot failure.
  18
  19 Also, change pll_type in 'ipq5018_pll_data' to
  20 CLK_ALPHA_PLL_TYPE_STROMER to better reflect that it is a Stromer
  21 PLL and change the apss_ipq_pll_probe() function accordingly.
  22
  23 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c#L67
  24
  25 Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018")
  26 Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
  27 ---
  28  drivers/clk/qcom/apss-ipq-pll.c | 30 +++++++++++++++++++++++++++---
  29  1 file changed, 27 insertions(+), 3 deletions(-)
  30
  31 --- a/drivers/clk/qcom/apss-ipq-pll.c
  32 +++ b/drivers/clk/qcom/apss-ipq-pll.c
  33 @@ -55,6 +55,29 @@ static struct clk_alpha_pll ipq_pll_huay
  34         },
  35  };
  36
  37 +static struct clk_alpha_pll ipq_pll_stromer = {
  38 +       .offset = 0x0,
  39 +       /*
  40 +        * Reuse CLK_ALPHA_PLL_TYPE_STROMER_PLUS register offsets.
  41 +        * Although this is a bit confusing, but the offset values
  42 +        * are correct nevertheless.
  43 +        */
  44 +       .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
  45 +       .flags = SUPPORTS_DYNAMIC_UPDATE,
  46 +       .clkr = {
  47 +               .enable_reg = 0x0,
  48 +               .enable_mask = BIT(0),
  49 +               .hw.init = &(const struct clk_init_data) {
  50 +                       .name = "a53pll",
  51 +                       .parent_data = &(const struct clk_parent_data) {
  52 +                               .fw_name = "xo",
  53 +                       },
  54 +                       .num_parents = 1,
  55 +                       .ops = &clk_alpha_pll_stromer_ops,
  56 +               },
  57 +       },
  58 +};
  59 +
  60  static struct clk_alpha_pll ipq_pll_stromer_plus = {
  61         .offset = 0x0,
  62         .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
  63 @@ -144,8 +167,8 @@ struct apss_pll_data {
  64  };
  65
  66  static const struct apss_pll_data ipq5018_pll_data = {
  67 -       .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
  68 -       .pll = &ipq_pll_stromer_plus,
  69 +       .pll_type = CLK_ALPHA_PLL_TYPE_STROMER,
  70 +       .pll = &ipq_pll_stromer,
  71         .pll_config = &ipq5018_pll_config,
  72  };
  73
  74 @@ -203,7 +226,8 @@ static int apss_ipq_pll_probe(struct pla
  75
  76         if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)
  77                 clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
  78 -       else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
  79 +       else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER ||
  80 +                data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
  81                 clk_stromer_pll_configure(data->pll, regmap, data->pll_config);
  82
  83         ret = devm_clk_register_regmap(dev, &data->pll->clkr);