git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From 3eac9319af62dbc56d1f06fcb240e4a092fa5b2f Mon Sep 17 00:00:00 2001
   2 From: Jianfeng Liu <liujianfeng1994@gmail.com>
   3 Date: Tue, 25 Feb 2025 11:08:48 +0800
   4 Subject: arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITX
   5
   6 Enable the HDMI port next to ethernet port.
   7
   8 Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
   9 Link: https://lore.kernel.org/r/20250225030904.2813023-1-liujianfeng1994@gmail.com
  10 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  11
  12 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
  13 +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
  14 @@ -11,6 +11,7 @@
  15  #include <dt-bindings/leds/common.h>
  16  #include <dt-bindings/pinctrl/rockchip.h>
  17  #include <dt-bindings/pwm/pwm.h>
  18 +#include <dt-bindings/soc/rockchip,vop2.h>
  19  #include "dt-bindings/usb/pd.h"
  20  #include "rk3588.dtsi"
  21
  22 @@ -72,6 +73,17 @@
  23                 };
  24         };
  25
  26 +       hdmi1-con {
  27 +               compatible = "hdmi-connector";
  28 +               type = "a";
  29 +
  30 +               port {
  31 +                       hdmi1_con_in: endpoint {
  32 +                               remote-endpoint = <&hdmi1_out_con>;
  33 +                       };
  34 +               };
  35 +       };
  36 +
  37         /* Unnamed gated oscillator: 100MHz,3.3V,3225 */
  38         pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
  39                 compatible = "gated-fixed-clock";
  40 @@ -261,6 +273,28 @@
  41         status = "okay";
  42  };
  43
  44 +&hdmi1 {
  45 +       pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
  46 +                    &hdmim1_tx1_scl &hdmim1_tx1_sda>;
  47 +       status = "okay";
  48 +};
  49 +
  50 +&hdmi1_in {
  51 +       hdmi1_in_vp1: endpoint {
  52 +               remote-endpoint = <&vp1_out_hdmi1>;
  53 +       };
  54 +};
  55 +
  56 +&hdmi1_out {
  57 +       hdmi1_out_con: endpoint {
  58 +               remote-endpoint = <&hdmi1_con_in>;
  59 +       };
  60 +};
  61 +
  62 +&hdptxphy1 {
  63 +       status = "okay";
  64 +};
  65 +
  66  &i2c0 {
  67         pinctrl-names = "default";
  68         pinctrl-0 = <&i2c0m2_xfer>;
  69 @@ -1208,3 +1242,18 @@
  70         rockchip,dp-lane-mux = <2 3>;
  71         status = "okay";
  72  };
  73 +
  74 +&vop {
  75 +       status = "okay";
  76 +};
  77 +
  78 +&vop_mmu {
  79 +       status = "okay";
  80 +};
  81 +
  82 +&vp1 {
  83 +       vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
  84 +               reg = <ROCKCHIP_VOP2_EP_HDMI1>;
  85 +               remote-endpoint = <&hdmi1_in_vp1>;
  86 +       };
  87 +};