dd7543d6f97dad105e3ca51806907c6e2f6e740c
[openwrt/staging/xback.git] /
1 From be378ebd6cfb8e369d4aa03a551e594d00debda5 Mon Sep 17 00:00:00 2001
2 From: Sky Huang <skylake.huang@mediatek.com>
3 Date: Thu, 13 Feb 2025 16:05:53 +0800
4 Subject: [PATCH 5/5] net: phy: mediatek: Move some macros to phy-lib for later
5 use
6
7 Move some macros to phy-lib because MediaTek's 2.5G built-in
8 ethernet PHY will also use them.
9
10 Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
11 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
12 Link: https://patch.msgid.link/20250213080553.921434-6-SkyLake.Huang@mediatek.com
13 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
14 ---
15 drivers/net/phy/mediatek/mtk-ge.c | 4 ----
16 drivers/net/phy/mediatek/mtk.h | 4 ++++
17 2 files changed, 4 insertions(+), 4 deletions(-)
18
19 --- a/drivers/net/phy/mediatek/mtk-ge.c
20 +++ b/drivers/net/phy/mediatek/mtk-ge.c
21 @@ -8,10 +8,6 @@
22 #define MTK_GPHY_ID_MT7530 0x03a29412
23 #define MTK_GPHY_ID_MT7531 0x03a29441
24
25 -#define MTK_PHY_PAGE_EXTENDED_1 0x0001
26 -#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
27 -#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
28 -
29 #define MTK_PHY_PAGE_EXTENDED_2 0x0002
30 #define MTK_PHY_PAGE_EXTENDED_3 0x0003
31 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
32 --- a/drivers/net/phy/mediatek/mtk.h
33 +++ b/drivers/net/phy/mediatek/mtk.h
34 @@ -8,7 +8,11 @@
35 #ifndef _MTK_EPHY_H_
36 #define _MTK_EPHY_H_
37
38 +#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
39 +#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
40 +
41 #define MTK_EXT_PAGE_ACCESS 0x1f
42 +#define MTK_PHY_PAGE_EXTENDED_1 0x0001
43 #define MTK_PHY_PAGE_STANDARD 0x0000
44 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
45