git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From 40d33d6d3c90eb104c66e05cdc00db61268c93f9 Mon Sep 17 00:00:00 2001
   2 From: Sky Huang <skylake.huang@mediatek.com>
   3 Date: Thu, 13 Feb 2025 16:05:51 +0800
   4 Subject: [PATCH 3/5] net: phy: mediatek: Add token ring set bit operation
   5  support
   6
   7 Previously in mtk-ge-soc.c, we set some register bits via token
   8 ring, which were implemented in three __phy_write().
   9 Now we can do the same thing via __mtk_tr_set_bits() helper.
  10
  11 Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
  12 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  13 Link: https://patch.msgid.link/20250213080553.921434-4-SkyLake.Huang@mediatek.com
  14 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  15 ---
  16  drivers/net/phy/mediatek/mtk-ge-soc.c  | 10 ++++++----
  17  drivers/net/phy/mediatek/mtk-phy-lib.c |  7 +++++++
  18  drivers/net/phy/mediatek/mtk.h         |  2 ++
  19  3 files changed, 15 insertions(+), 4 deletions(-)
  20
  21 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c
  22 +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
  23 @@ -62,6 +62,10 @@
  24  /* MasDSPreadyTime */
  25  #define MASTER_DSP_READY_TIME_MASK             GENMASK(14, 7)
  26
  27 +/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */
  28 +/* EnabRandUpdTrig */
  29 +#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER   BIT(8)
  30 +
  31  /* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */
  32  /* ResetSyncOffset */
  33  #define RESET_SYNC_OFFSET_MASK                 GENMASK(11, 8)
  34 @@ -789,10 +793,8 @@ static void mt798x_phy_common_finetune(s
  35                         FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) |
  36                         FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18));
  37
  38 -       /* EnabRandUpdTrig = 1 */
  39 -       __phy_write(phydev, 0x11, 0x2f00);
  40 -       __phy_write(phydev, 0x12, 0xe);
  41 -       __phy_write(phydev, 0x10, 0x8fb0);
  42 +       __mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18,
  43 +                         ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER);
  44
  45         __mtk_tr_modify(phydev, 0x0, 0x7, 0x15,
  46                         NORMAL_MSE_LO_THRESH_MASK,
  47 --- a/drivers/net/phy/mediatek/mtk-phy-lib.c
  48 +++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
  49 @@ -69,6 +69,13 @@ void mtk_tr_modify(struct phy_device *ph
  50  }
  51  EXPORT_SYMBOL_GPL(mtk_tr_modify);
  52
  53 +void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
  54 +                      u8 data_addr, u32 set)
  55 +{
  56 +       __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, 0, set);
  57 +}
  58 +EXPORT_SYMBOL_GPL(__mtk_tr_set_bits);
  59 +
  60  int mtk_phy_read_page(struct phy_device *phydev)
  61  {
  62         return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
  63 --- a/drivers/net/phy/mediatek/mtk.h
  64 +++ b/drivers/net/phy/mediatek/mtk.h
  65 @@ -72,6 +72,8 @@ void __mtk_tr_modify(struct phy_device *
  66                      u8 data_addr, u32 mask, u32 set);
  67  void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
  68                    u8 data_addr, u32 mask, u32 set);
  69 +void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
  70 +                      u8 data_addr, u32 set);
  71
  72  int mtk_phy_read_page(struct phy_device *phydev);
  73  int mtk_phy_write_page(struct phy_device *phydev, int page);