git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From 491cb9c5084790aafa02e843349492c284373231 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Thu, 9 Jan 2025 00:30:45 +0100
   4 Subject: [PATCH 6/6] PCI: mediatek-gen3: Avoid PCIe resetting via PERST# for
   5  Airoha EN7581 SoC
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 Airoha EN7581 has a hw bug asserting/releasing PERST# signal causing
  11 occasional PCIe link down issues. In order to overcome the problem,
  12 PERST# signal is not asserted/released during device probe or
  13 suspend/resume phase and the PCIe block is reset using
  14 en7523_reset_assert() and en7581_pci_enable().
  15
  16 Introduce flags field in the mtk_gen3_pcie_pdata struct in order to
  17 specify per-SoC capabilities.
  18
  19 Link: https://lore.kernel.org/r/20250109-pcie-en7581-rst-fix-v4-1-4a45c89fb143@kernel.org
  20 Tested-by: Hui Ma <hui.ma@airoha.com>
  21 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  22 Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
  23 ---
  24  drivers/pci/controller/pcie-mediatek-gen3.c | 59 ++++++++++++++-------
  25  1 file changed, 41 insertions(+), 18 deletions(-)
  26
  27 --- a/drivers/pci/controller/pcie-mediatek-gen3.c
  28 +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
  29 @@ -127,10 +127,18 @@
  30
  31  struct mtk_gen3_pcie;
  32
  33 +enum mtk_gen3_pcie_flags {
  34 +       SKIP_PCIE_RSTB  = BIT(0), /* Skip PERST# assertion during device
  35 +                                  * probing or suspend/resume phase to
  36 +                                  * avoid hw bugs/issues.
  37 +                                  */
  38 +};
  39 +
  40  /**
  41   * struct mtk_gen3_pcie_pdata - differentiate between host generations
  42   * @power_up: pcie power_up callback
  43   * @phy_resets: phy reset lines SoC data.
  44 + * @flags: pcie device flags.
  45   */
  46  struct mtk_gen3_pcie_pdata {
  47         int (*power_up)(struct mtk_gen3_pcie *pcie);
  48 @@ -138,6 +146,7 @@ struct mtk_gen3_pcie_pdata {
  49                 const char *id[MAX_NUM_PHY_RESETS];
  50                 int num_resets;
  51         } phy_resets;
  52 +       u32 flags;
  53  };
  54
  55  /**
  56 @@ -404,22 +413,33 @@ static int mtk_pcie_startup_port(struct
  57         val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
  58         writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);
  59
  60 -       /* Assert all reset signals */
  61 -       val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
  62 -       val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
  63 -       writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
  64 -
  65         /*
  66 -        * Described in PCIe CEM specification sections 2.2 (PERST# Signal)
  67 -        * and 2.2.1 (Initial Power-Up (G3 to S0)).
  68 -        * The deassertion of PERST# should be delayed 100ms (TPVPERL)
  69 -        * for the power and clock to become stable.
  70 +        * Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal
  71 +        * causing occasional PCIe link down. In order to overcome the issue,
  72 +        * PCIE_RSTB signals are not asserted/released at this stage and the
  73 +        * PCIe block is reset using en7523_reset_assert() and
  74 +        * en7581_pci_enable().
  75          */
  76 -       msleep(100);
  77 -
  78 -       /* De-assert reset signals */
  79 -       val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
  80 -       writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
  81 +       if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
  82 +               /* Assert all reset signals */
  83 +               val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
  84 +               val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
  85 +                      PCIE_PE_RSTB;
  86 +               writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
  87 +
  88 +               /*
  89 +                * Described in PCIe CEM specification revision 6.0.
  90 +                *
  91 +                * The deassertion of PERST# should be delayed 100ms (TPVPERL)
  92 +                * for the power and clock to become stable.
  93 +                */
  94 +               msleep(PCIE_T_PVPERL_MS);
  95 +
  96 +               /* De-assert reset signals */
  97 +               val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
  98 +                        PCIE_PE_RSTB);
  99 +               writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
 100 +       }
 101
 102         /* Check if the link is up or not */
 103         err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
 104 @@ -1178,10 +1198,12 @@ static int mtk_pcie_suspend_noirq(struct
 105                 return err;
 106         }
 107
 108 -       /* Pull down the PERST# pin */
 109 -       val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
 110 -       val |= PCIE_PE_RSTB;
 111 -       writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
 112 +       if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {
 113 +               /* Assert the PERST# pin */
 114 +               val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);
 115 +               val |= PCIE_PE_RSTB;
 116 +               writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
 117 +       }
 118
 119         dev_dbg(pcie->dev, "entered L2 states successfully");
 120
 121 @@ -1232,6 +1254,7 @@ static const struct mtk_gen3_pcie_pdata
 122                 .id[2] = "phy-lane2",
 123                 .num_resets = 3,
 124         },
 125 +       .flags = SKIP_PCIE_RSTB,
 126  };
 127
 128  static const struct of_device_id mtk_pcie_of_match[] = {