1 From e00fc3d6e7c2d0b2ab5cf03a576df39cd94479aa Mon Sep 17 00:00:00 2001
2 From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
3 Date: Tue, 4 Feb 2025 16:35:47 +0100
4 Subject: [PATCH] dt-bindings: rng: add binding for Rockchip RK3588 RNG
6 The Rockchip RK3588 SoC has two hardware RNGs accessible to the
7 non-secure world: an RNG in the Crypto IP, and a standalone RNG that is
10 Add a binding for this new standalone RNG. It is distinct hardware from
11 the existing rockchip,rk3568-rng, and therefore gets its own binding as
12 the two hardware IPs are unrelated other than both being made by the
15 The RNG is capable of firing an interrupt when entropy is ready.
17 The reset is optional, as the hardware does a power-on reset, and
18 functions without the software manually resetting it.
20 Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
21 Acked-by: Conor Dooley <conor.dooley@microchip.com>
22 Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
24 .../bindings/rng/rockchip,rk3588-rng.yaml | 60 +++++++++++++++++++
26 2 files changed, 61 insertions(+)
27 create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml
30 +++ b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml
32 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
35 +$id: http://devicetree.org/schemas/rng/rockchip,rk3588-rng.yaml#
36 +$schema: http://devicetree.org/meta-schemas/core.yaml#
38 +title: Rockchip RK3588 TRNG
40 +description: True Random Number Generator on Rockchip RK3588 SoC
43 + - Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
48 + - rockchip,rk3588-rng
55 + - description: TRNG AHB clock
69 +additionalProperties: false
73 + #include <dt-bindings/clock/rockchip,rk3588-cru.h>
74 + #include <dt-bindings/interrupt-controller/arm-gic.h>
75 + #include <dt-bindings/interrupt-controller/irq.h>
76 + #include <dt-bindings/reset/rockchip,rk3588-cru.h>
78 + #address-cells = <2>;
82 + compatible = "rockchip,rk3588-rng";
83 + reg = <0x0 0xfe378000 0x0 0x200>;
84 + interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
85 + clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
86 + resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>;