git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From b9dfb5636bc5eb9b783b88b8388dc7d1f41d6498 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Tue, 17 Dec 2024 16:39:59 +0800
   4 Subject: [PATCH 09/10] net: mediatek: don't enable GDMA cpu bridge
   5  unconditionally for NETSYSv3
   6
   7 Enable GDMA cpu bridge only when 10Gb interface is enabled for GMAC other
   8 than GMAC0, or when MT7988 internal switch is used.
   9
  10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  11 ---
  12  drivers/net/mtk_eth.c | 12 +++++++++---
  13  1 file changed, 9 insertions(+), 3 deletions(-)
  14
  15 --- a/drivers/net/mtk_eth.c
  16 +++ b/drivers/net/mtk_eth.c
  17 @@ -1762,10 +1762,16 @@ static int mtk_eth_start(struct udevice
  18                 if (priv->sw == SW_MT7988 && priv->gmac_id == 0) {
  19                         mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG,
  20                                        GDMA_BRIDGE_TO_CPU);
  21 -               }
  22
  23 -               mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
  24 -                              GDMA_CPU_BRIDGE_EN);
  25 +                       mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
  26 +                                      GDMA_CPU_BRIDGE_EN);
  27 +               } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
  28 +                           priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
  29 +                           priv->phy_interface == PHY_INTERFACE_MODE_XGMII) &&
  30 +                          priv->gmac_id != 0) {
  31 +                       mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
  32 +                                      GDMA_CPU_BRIDGE_EN);
  33 +               }
  34         }
  35
  36         udelay(500);