git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From fbea35a661ed100cee2f3bab8015fb0155508106 Mon Sep 17 00:00:00 2001
   2 From: Chukun Pan <amadeus@jmu.edu.cn>
   3 Date: Sat, 8 Mar 2025 17:30:08 +0800
   4 Subject: [PATCH] arm64: dts: rockchip: Move rk3568 PCIe3 MSI to use GIC ITS
   5
   6 Following commit b956c9de9175 ("arm64: dts: rockchip: rk356x: Move
   7 PCIe MSI to use GIC ITS instead of MBI"), change the PCIe3 controller's
   8 MSI on rk3568 to use ITS, so that all MSI-X can work properly.
   9
  10 Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
  11 Link: https://lore.kernel.org/r/20250308093008.568437-2-amadeus@jmu.edu.cn
  12 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  13 ---
  14  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 8 ++++----
  15  1 file changed, 4 insertions(+), 4 deletions(-)
  16
  17 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
  18 +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
  19 @@ -64,7 +64,7 @@
  20                 compatible = "rockchip,rk3568-pcie";
  21                 #address-cells = <3>;
  22                 #size-cells = <2>;
  23 -               bus-range = <0x0 0xf>;
  24 +               bus-range = <0x10 0x1f>;
  25                 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
  26                          <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
  27                          <&cru CLK_PCIE30X1_AUX_NDFT>;
  28 @@ -87,7 +87,7 @@
  29                 num-ib-windows = <6>;
  30                 num-ob-windows = <2>;
  31                 max-link-speed = <3>;
  32 -               msi-map = <0x0 &gic 0x1000 0x1000>;
  33 +               msi-map = <0x1000 &its 0x1000 0x1000>;
  34                 num-lanes = <1>;
  35                 phys = <&pcie30phy>;
  36                 phy-names = "pcie-phy";
  37 @@ -117,7 +117,7 @@
  38                 compatible = "rockchip,rk3568-pcie";
  39                 #address-cells = <3>;
  40                 #size-cells = <2>;
  41 -               bus-range = <0x0 0xf>;
  42 +               bus-range = <0x20 0x2f>;
  43                 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
  44                          <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
  45                          <&cru CLK_PCIE30X2_AUX_NDFT>;
  46 @@ -140,7 +140,7 @@
  47                 num-ib-windows = <6>;
  48                 num-ob-windows = <2>;
  49                 max-link-speed = <3>;
  50 -               msi-map = <0x0 &gic 0x2000 0x1000>;
  51 +               msi-map = <0x2000 &its 0x2000 0x1000>;
  52                 num-lanes = <2>;
  53                 phys = <&pcie30phy>;
  54                 phy-names = "pcie-phy";