git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From 4786eff288bcc77a5dbc2be2308f46f70e58600d Mon Sep 17 00:00:00 2001
   2 From: Sky Huang <skylake.huang@mediatek.com>
   3 Date: Thu, 13 Feb 2025 16:05:52 +0800
   4 Subject: [PATCH 4/5] net: phy: mediatek: Add token ring clear bit operation
   5  support
   6
   7 Similar to __mtk_tr_set_bits() support. Previously in mtk-ge-soc.c,
   8 we clear some register bits via token ring, which were also implemented
   9 in three __phy_write(). Now we can do the same thing via
  10 __mtk_tr_clr_bits() helper.
  11
  12 Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
  13 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  14 Link: https://patch.msgid.link/20250213080553.921434-5-SkyLake.Huang@mediatek.com
  15 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  16 ---
  17  drivers/net/phy/mediatek/mtk-ge-soc.c  | 30 +++++++++++++++-----------
  18  drivers/net/phy/mediatek/mtk-phy-lib.c |  7 ++++++
  19  drivers/net/phy/mediatek/mtk.h         |  2 ++
  20  3 files changed, 27 insertions(+), 12 deletions(-)
  21
  22 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c
  23 +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
  24 @@ -76,6 +76,10 @@
  25  /* FfeUpdGainForce */
  26  #define FFE_UPDATE_GAIN_FORCE                  BIT(6)
  27
  28 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */
  29 +/* TrFreeze */
  30 +#define TR_FREEZE_MASK                         GENMASK(11, 0)
  31 +
  32  /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */
  33  /* SS: Steady-state, KP: Proportional Gain */
  34  /* SSTrKp100 */
  35 @@ -91,6 +95,11 @@
  36  /* SSTrKf1000Slv */
  37  #define SS_TR_KF1000_SLAVE_MASK                        GENMASK(6, 4)
  38
  39 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */
  40 +/* clear this bit if wanna select from AFE */
  41 +/* Regsigdet_sel_1000 */
  42 +#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE       BIT(4)
  43 +
  44  /* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */
  45  /* RegEEE_st2TrKf1000 */
  46  #define EEE1000_STAGE2_TR_KF_MASK              GENMASK(13, 11)
  47 @@ -113,6 +122,10 @@
  48  /* RegEEE100Stg1_tar */
  49  #define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0)
  50
  51 +/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */
  52 +/* REGEEE_wake_slv_tr_wait_dfesigdet_en */
  53 +#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN    BIT(11)
  54 +
  55  #define ANALOG_INTERNAL_OPERATION_MAX_US       20
  56  #define TXRESERVE_MIN                          0
  57  #define TXRESERVE_MAX                          7
  58 @@ -805,10 +818,7 @@ static void mt798x_phy_common_finetune(s
  59                         FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) |
  60                                    FFE_UPDATE_GAIN_FORCE);
  61
  62 -       /* TrFreeze = 0 (mt7988 default) */
  63 -       __phy_write(phydev, 0x11, 0x0);
  64 -       __phy_write(phydev, 0x12, 0x0);
  65 -       __phy_write(phydev, 0x10, 0x9686);
  66 +       __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK);
  67
  68         __mtk_tr_modify(phydev, 0x2, 0xd, 0x6,
  69                         SS_TR_KP100_MASK | SS_TR_KF100_MASK |
  70 @@ -1009,10 +1019,8 @@ static void mt798x_phy_eee(struct phy_de
  71                          MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
  72
  73         phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
  74 -       /* Regsigdet_sel_1000 = 0 */
  75 -       __phy_write(phydev, 0x11, 0xb);
  76 -       __phy_write(phydev, 0x12, 0x0);
  77 -       __phy_write(phydev, 0x10, 0x9690);
  78 +       __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8,
  79 +                         EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE);
  80
  81         __mtk_tr_modify(phydev, 0x2, 0xd, 0xd,
  82                         EEE1000_STAGE2_TR_KF_MASK,
  83 @@ -1036,10 +1044,8 @@ static void mt798x_phy_eee(struct phy_de
  84                         FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK,
  85                                    0x10));
  86
  87 -       /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
  88 -       __phy_write(phydev, 0x11, 0x1463);
  89 -       __phy_write(phydev, 0x12, 0x0);
  90 -       __phy_write(phydev, 0x10, 0x96ca);
  91 +       __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25,
  92 +                         WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN);
  93
  94         __mtk_tr_modify(phydev, 0x1, 0xf, 0x0,
  95                         DFE_TAIL_EANBLE_VGA_TRHESH_1000,
  96 --- a/drivers/net/phy/mediatek/mtk-phy-lib.c
  97 +++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
  98 @@ -76,6 +76,13 @@ void __mtk_tr_set_bits(struct phy_device
  99  }
 100  EXPORT_SYMBOL_GPL(__mtk_tr_set_bits);
 101
 102 +void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
 103 +                      u8 data_addr, u32 clr)
 104 +{
 105 +       __mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, clr, 0);
 106 +}
 107 +EXPORT_SYMBOL_GPL(__mtk_tr_clr_bits);
 108 +
 109  int mtk_phy_read_page(struct phy_device *phydev)
 110  {
 111         return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
 112 --- a/drivers/net/phy/mediatek/mtk.h
 113 +++ b/drivers/net/phy/mediatek/mtk.h
 114 @@ -74,6 +74,8 @@ void mtk_tr_modify(struct phy_device *ph
 115                    u8 data_addr, u32 mask, u32 set);
 116  void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
 117                        u8 data_addr, u32 set);
 118 +void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
 119 +                      u8 data_addr, u32 clr);
 120
 121  int mtk_phy_read_page(struct phy_device *phydev);
 122  int mtk_phy_write_page(struct phy_device *phydev, int page);