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1 From d12722830ea4f562e91586927ec21b64d0369544 Mon Sep 17 00:00:00 2001
2 From: Bitterblue Smith <rtl8821cerfe2@gmail.com>
3 Date: Wed, 23 Oct 2024 17:00:59 +0300
4 Subject: [PATCH] wifi: rtw88: Add some definitions for RTL8821AU/RTL8812AU
5
6 Add 8821A and 8812A chip type enums.
7
8 Add cck_high_power member to struct rtw_hal. This will be used to
9 calculate the RX signal strength of RTL8812AU.
10
11 Add various register definitions which will be used by the new drivers.
12
13 Move some existing register definitions from rtw8821c.h and rtw8822b.h.
14 They were duplicated in those headers and will also be used by the new
15 drivers.
16
17 Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
18 Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
19 Link: https://patch.msgid.link/9279a9cd-6f86-4dc3-a095-7c36cb9b9d06@gmail.com
20 ---
21 drivers/net/wireless/realtek/rtw88/main.h | 3 +
22 drivers/net/wireless/realtek/rtw88/reg.h | 174 ++++++++++++++++++
23 drivers/net/wireless/realtek/rtw88/rtw8821c.h | 24 ---
24 drivers/net/wireless/realtek/rtw88/rtw8822b.h | 12 --
25 4 files changed, 177 insertions(+), 36 deletions(-)
26
27 --- a/drivers/net/wireless/realtek/rtw88/main.h
28 +++ b/drivers/net/wireless/realtek/rtw88/main.h
29 @@ -189,6 +189,8 @@ enum rtw_chip_type {
30 RTW_CHIP_TYPE_8723D,
31 RTW_CHIP_TYPE_8821C,
32 RTW_CHIP_TYPE_8703B,
33 + RTW_CHIP_TYPE_8821A,
34 + RTW_CHIP_TYPE_8812A,
35 };
36
37 enum rtw_tx_queue_type {
38 @@ -1934,6 +1936,7 @@ struct rtw_hal {
39 u32 antenna_rx;
40 u8 bfee_sts_cap;
41 bool txrx_1ss;
42 + bool cck_high_power;
43
44 /* protect tx power section */
45 struct mutex tx_power_mutex;
46 --- a/drivers/net/wireless/realtek/rtw88/reg.h
47 +++ b/drivers/net/wireless/realtek/rtw88/reg.h
48 @@ -9,6 +9,7 @@
49 #define BIT_FEN_EN_25_1 BIT(13)
50 #define BIT_FEN_ELDR BIT(12)
51 #define BIT_FEN_CPUEN BIT(2)
52 +#define BIT_FEN_USBA BIT(2)
53 #define BIT_FEN_BB_GLB_RST BIT(1)
54 #define BIT_FEN_BB_RSTB BIT(0)
55 #define BIT_R_DIS_PRST BIT(6)
56 @@ -16,6 +17,10 @@
57 #define REG_SYS_PW_CTRL 0x0004
58 #define BIT_PFM_WOWL BIT(3)
59 #define BIT_APFM_OFFMAC BIT(9)
60 +#define REG_APS_FSMCO 0x0004
61 +#define APS_FSMCO_MAC_ENABLE BIT(8)
62 +#define APS_FSMCO_MAC_OFF BIT(9)
63 +#define APS_FSMCO_HW_POWERDOWN BIT(15)
64 #define REG_SYS_CLK_CTRL 0x0008
65 #define BIT_CPU_CLK_EN BIT(14)
66
67 @@ -58,6 +63,8 @@
68 #define BIT_SHIFT_LDO25_VOLTAGE 4
69 #define BIT_LDO25_EN BIT(7)
70
71 +#define REG_ACLK_MON 0x3e
72 +
73 #define REG_GPIO_MUXCFG 0x0040
74 #define BIT_FSPI_EN BIT(19)
75 #define BIT_EN_SIC BIT(12)
76 @@ -90,6 +97,8 @@
77 #define BIT_USB_SUS_DIS BIT(8)
78 #define BIT_SDIO_PAD_E5 BIT(18)
79
80 +#define REG_RF_B_CTRL 0x76
81 +
82 #define REG_AFE_CTRL_4 0x0078
83 #define BIT_CK320M_AFE_EN BIT(4)
84 #define BIT_EN_SYN BIT(15)
85 @@ -134,6 +143,11 @@
86 #define REG_PMC_DBG_CTRL1 0xa8
87 #define BITS_PMC_BT_IQK_STS GENMASK(22, 21)
88
89 +#define REG_HIMR0 0xb0
90 +#define REG_HISR0 0xb4
91 +#define REG_HIMR1 0xb8
92 +#define REG_HISR1 0xbc
93 +
94 #define REG_PAD_CTRL2 0x00C4
95 #define BIT_RSM_EN_V1 BIT(16)
96 #define BIT_NO_PDN_CHIPOFF_V1 BIT(17)
97 @@ -185,6 +199,15 @@
98 #define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
99 BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
100 BIT_MACTXEN | BIT_MACRXEN)
101 +#define REG_PBP 0x104
102 +#define PBP_RX_MASK 0x0f
103 +#define PBP_TX_MASK 0xf0
104 +#define PBP_64 0x0
105 +#define PBP_128 0x1
106 +#define PBP_256 0x2
107 +#define PBP_512 0x3
108 +#define PBP_1024 0x4
109 +
110 #define BIT_SHIFT_TXDMA_VOQ_MAP 4
111 #define BIT_MASK_TXDMA_VOQ_MAP 0x3
112 #define BIT_TXDMA_VOQ_MAP(x) \
113 @@ -256,6 +279,8 @@
114 #define REG_HMEBOX1 0x01D4
115 #define REG_HMEBOX2 0x01D8
116 #define REG_HMEBOX3 0x01DC
117 +#define REG_LLT_INIT 0x01E0
118 +#define BIT_LLT_WRITE_ACCESS BIT(30)
119 #define REG_HMEBOX0_EX 0x01F0
120 #define REG_HMEBOX1_EX 0x01F4
121 #define REG_HMEBOX2_EX 0x01F8
122 @@ -298,6 +323,7 @@
123
124 #define REG_AUTO_LLT 0x0224
125 #define BIT_AUTO_INIT_LLT BIT(16)
126 +#define REG_DWBCN1_CTRL 0x0228
127 #define REG_RQPN_CTRL_1 0x0228
128 #define REG_RQPN_CTRL_2 0x022C
129 #define BIT_LD_RQPN BIT(31)
130 @@ -329,6 +355,7 @@
131 #define BIT_DMA_BURST_SIZE_1024 0
132
133 #define REG_RXPKTNUM 0x02B0
134 +#define REG_EARLY_MODE_CONTROL 0x02BC
135
136 #define REG_INT_MIG 0x0304
137 #define REG_HCI_MIX_CFG 0x03FC
138 @@ -336,6 +363,7 @@
139
140 #define REG_BCNQ_INFO 0x0418
141 #define BIT_MGQ_CPU_EMPTY BIT(24)
142 +#define REG_TXPKT_EMPTY 0x041A
143 #define REG_FWHW_TXQ_CTRL 0x0420
144 #define BIT_EN_BCNQ_DL BIT(22)
145 #define BIT_EN_WR_FREE_TAIL BIT(20)
146 @@ -362,10 +390,12 @@
147 #define REG_AMPDU_MAX_TIME_V1 0x0455
148 #define REG_BCNQ1_BDNY_V1 0x0456
149 #define REG_AMPDU_MAX_TIME 0x0456
150 +#define REG_AMPDU_MAX_LENGTH 0x0458
151 #define REG_WMAC_LBK_BF_HD 0x045D
152 #define REG_TX_HANG_CTRL 0x045E
153 #define BIT_EN_GNT_BT_AWAKE BIT(3)
154 #define BIT_EN_EOF_V1 BIT(2)
155 +#define REG_FAST_EDCA_CTRL 0x0460
156 #define REG_DATA_SC 0x0483
157 #define REG_ARFR2_V1 0x048C
158 #define REG_ARFRH2_V1 0x0490
159 @@ -390,6 +420,8 @@
160 #define REG_PRECNT_CTRL 0x04E5
161 #define BIT_BTCCA_CTRL (BIT(0) | BIT(1))
162 #define BIT_EN_PRECNT BIT(11)
163 +#define REG_TX_RPT_CTRL 0x04EC
164 +#define REG_TX_RPT_TIME 0x04F0
165 #define REG_DUMMY_PAGE4_V1 0x04FC
166
167 #define REG_EDCA_VO_PARAM 0x0500
168 @@ -400,6 +432,7 @@
169 #define BIT_MASK_CWMAX GENMASK(15, 12)
170 #define BIT_MASK_CWMIN GENMASK(11, 8)
171 #define BIT_MASK_AIFS GENMASK(7, 0)
172 +#define REG_BCNTCFG 0x0510
173 #define REG_PIFS 0x0512
174 #define REG_SIFS 0x0514
175 #define BIT_SHIFT_SIFS_OFDM_CTX 8
176 @@ -526,6 +559,8 @@
177 #define REG_BT_COEX_V2 0x0762
178 #define BIT_GNT_BT_POLARITY BIT(12)
179 #define BIT_LTE_COEX_EN BIT(7)
180 +#define REG_GNT_BT 0x0765
181 +#define BIT_PTA_SW_CTL GENMASK(4, 3)
182 #define REG_BT_COEX_ENH_INTR_CTRL 0x76E
183 #define BIT_R_GRANTALL_WLMASK BIT(3)
184 #define BIT_STATIS_BT_EN BIT(2)
185 @@ -543,14 +578,43 @@
186 #define REG_FPGA0_RFMOD 0x0800
187 #define BIT_CCKEN BIT(24)
188 #define BIT_OFDMEN BIT(25)
189 +#define REG_CCK_RPT_FORMAT 0x0804
190 +#define BIT_CCK_RPT_FORMAT BIT(16)
191 +#define REG_RXPSEL 0x0808
192 +#define BIT_RX_PSEL_RST (BIT(28) | BIT(29))
193 +#define REG_TXPSEL 0x080C
194 #define REG_RX_GAIN_EN 0x081c
195 +#define REG_CCASEL 0x082C
196 +#define REG_PDMFTH 0x0830
197 +#define REG_BWINDICATION 0x0834
198 +#define REG_CCA2ND 0x0838
199 +#define REG_L1PKTH 0x0848
200 +#define REG_CLKTRK 0x0860
201 +#define REG_ADCCLK 0x08AC
202 +#define REG_HSSI_READ 0x08B0
203 +#define REG_FPGA0_XCD_RF_PARA 0x08B4
204 +#define REG_RX_MCS_LIMIT 0x08BC
205 +#define REG_ADC160 0x08C4
206 +#define REG_ANTSEL_SW 0x0900
207 +#define REG_DAC_RSTB 0x090c
208 +#define REG_SINGLE_TONE_CONT_TX 0x0914
209
210 #define REG_RFE_CTRL_E 0x0974
211 #define REG_2ND_CCA_CTRL 0x0976
212 +#define REG_IQK_COM00 0x0978
213 +#define REG_IQK_COM32 0x097c
214 +#define REG_IQK_COM64 0x0980
215 +#define REG_IQK_COM96 0x0984
216 +
217 +#define REG_FAS 0x09a4
218 +#define REG_RXSB 0x0a00
219 +#define REG_CCK_RX 0x0a04
220 +#define REG_CCK_PD_TH 0x0a0a
221
222 #define REG_CCK0_FAREPORT 0xa2c
223 #define BIT_CCK0_2RX BIT(18)
224 #define BIT_CCK0_MRC BIT(22)
225 +#define REG_FA_CCK 0x0a5c
226
227 #define REG_DIS_DPD 0x0a70
228 #define DIS_DPD_MASK GENMASK(9, 0)
229 @@ -566,13 +630,109 @@
230 #define DIS_DPD_RATEVHT2SS_MCS1 BIT(9)
231 #define DIS_DPD_RATEALL GENMASK(9, 0)
232
233 +#define REG_CNTRST 0x0b58
234 +
235 +#define REG_3WIRE_SWA 0x0c00
236 +#define REG_RX_IQC_AB_A 0x0c10
237 +#define REG_TXSCALE_A 0x0c1c
238 +#define BB_SWING_MASK GENMASK(31, 21)
239 +#define REG_TX_AGC_A_CCK_11_CCK_1 0xc20
240 +#define REG_TX_AGC_A_OFDM18_OFDM6 0xc24
241 +#define REG_TX_AGC_A_OFDM54_OFDM24 0xc28
242 +#define REG_TX_AGC_A_MCS3_MCS0 0xc2c
243 +#define REG_TX_AGC_A_MCS7_MCS4 0xc30
244 +#define REG_TX_AGC_A_MCS11_MCS8 0xc34
245 +#define REG_TX_AGC_A_MCS15_MCS12 0xc38
246 +#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0 0xc3c
247 +#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4 0xc40
248 +#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8 0xc44
249 +#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2 0xc48
250 +#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6 0xc4c
251 +#define REG_RXIGI_A 0x0c50
252 +#define REG_TX_PWR_TRAINING_A 0x0c54
253 +#define REG_CK_MONHA 0x0c5c
254 +#define REG_AFE_PWR1_A 0x0c60
255 +#define REG_AFE_PWR2_A 0x0c64
256 +#define REG_RX_WAIT_CCA_TX_CCK_RFON_A 0x0c68
257 +#define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80
258 +#define REG_OFDM0_A_TX_AFE 0x0c84
259 +#define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88
260 +#define REG_TSSI_TRK_SW 0x0c8c
261 +#define REG_LSSI_WRITE_A 0x0c90
262 +#define REG_PREDISTA 0x0c90
263 +#define REG_TXAGCIDX 0x0c94
264 +
265 +#define REG_RFE_PINMUX_A 0x0cb0
266 +#define REG_RFE_INV_A 0x0cb4
267 #define REG_RFE_CTRL8 0x0cb4
268 #define BIT_MASK_RFE_SEL89 GENMASK(7, 0)
269 +#define PTA_CTRL_PIN 0x66
270 +#define DPDT_CTRL_PIN 0x77
271 +#define RFE_INV_MASK 0x3ff00000
272 +#define REG_RFECTL_A 0x0cb8
273 #define REG_RFE_INV8 0x0cbd
274 #define BIT_MASK_RFE_INV89 GENMASK(1, 0)
275 #define REG_RFE_INV16 0x0cbe
276 #define BIT_RFE_BUF_EN BIT(3)
277
278 +#define REG_IQK_DPD_CFG 0x0cc4
279 +#define REG_CFG_PMPD 0x0cc8
280 +#define REG_IQC_Y 0x0ccc
281 +#define REG_IQC_X 0x0cd4
282 +#define REG_INTPO_SETA 0x0ce8
283 +
284 +#define REG_IQKA_END 0x0d00
285 +#define REG_PI_READ_A 0x0d04
286 +#define REG_SI_READ_A 0x0d08
287 +#define REG_IQKB_END 0x0d40
288 +#define REG_PI_READ_B 0x0d44
289 +#define REG_SI_READ_B 0x0d48
290 +
291 +#define REG_3WIRE_SWB 0x0e00
292 +#define REG_RX_IQC_AB_B 0x0e10
293 +#define REG_TXSCALE_B 0x0e1c
294 +#define REG_TX_AGC_B_CCK_11_CCK_1 0xe20
295 +#define REG_TX_AGC_B_OFDM18_OFDM6 0xe24
296 +#define REG_TX_AGC_B_OFDM54_OFDM24 0xe28
297 +#define REG_TX_AGC_B_MCS3_MCS0 0xe2c
298 +#define REG_TX_AGC_B_MCS7_MCS4 0xe30
299 +#define REG_TX_AGC_B_MCS11_MCS8 0xe34
300 +#define REG_TX_AGC_B_MCS15_MCS12 0xe38
301 +#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0 0xe3c
302 +#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4 0xe40
303 +#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8 0xe44
304 +#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2 0xe48
305 +#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6 0xe4c
306 +#define REG_RXIGI_B 0x0e50
307 +#define REG_TX_PWR_TRAINING_B 0x0e54
308 +#define REG_CK_MONHB 0x0e5c
309 +#define REG_AFE_PWR1_B 0x0e60
310 +#define REG_AFE_PWR2_B 0x0e64
311 +#define REG_RX_WAIT_CCA_TX_CCK_RFON_B 0x0e68
312 +#define REG_TXTONEB 0x0e80
313 +#define REG_RXTONEB 0x0e84
314 +#define REG_TXPITMB 0x0e88
315 +#define REG_RXPITMB 0x0e8c
316 +#define REG_LSSI_WRITE_B 0x0e90
317 +#define REG_PREDISTB 0x0e90
318 +#define REG_INIDLYB 0x0e94
319 +#define REG_RFE_PINMUX_B 0x0eb0
320 +#define REG_RFE_INV_B 0x0eb4
321 +#define REG_RFECTL_B 0x0eb8
322 +#define REG_BPBDB 0x0ec4
323 +#define REG_PHYTXONB 0x0ec8
324 +#define REG_IQKYB 0x0ecc
325 +#define REG_IQKXB 0x0ed4
326 +#define REG_INTPO_SETB 0x0ee8
327 +
328 +#define REG_CRC_CCK 0x0f04
329 +#define REG_CCA_OFDM 0x0f08
330 +#define REG_CRC_VHT 0x0f0c
331 +#define REG_CRC_HT 0x0f10
332 +#define REG_CRC_OFDM 0x0f14
333 +#define REG_FA_OFDM 0x0f48
334 +#define REG_CCA_CCK 0x0fcc
335 +
336 #define REG_ANAPARSW_MAC_0 0x1010
337 #define BIT_CF_L_V2 GENMASK(29, 28)
338
339 @@ -709,6 +869,10 @@
340
341 #define REG_IGN_GNTBT4 0x4160
342
343 +#define REG_USB_MOD 0xf008
344 +#define REG_USB3_RXITV 0xf050
345 +#define REG_USB_HRPWM 0xfe58
346 +
347 #define RF_MODE 0x00
348 #define RF_MODOPT 0x01
349 #define RF_WLINT 0x01
350 @@ -716,7 +880,13 @@
351 #define RF_DTXLOK 0x08
352 #define RF_CFGCH 0x18
353 #define BIT_BAND GENMASK(18, 16)
354 +#define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
355 +#define RF18_CHANNEL_MASK (MASKBYTE0)
356 +#define RF18_RFSI_MASK (BIT(18) | BIT(17))
357 #define RF_RCK 0x1d
358 +#define RF_MODE_TABLE_ADDR 0x30
359 +#define RF_MODE_TABLE_DATA0 0x31
360 +#define RF_MODE_TABLE_DATA1 0x32
361 #define RF_LUTWA 0x33
362 #define RF_LUTWD1 0x3e
363 #define RF_LUTWD0 0x3f
364 @@ -725,10 +895,14 @@
365 #define RF_T_METER 0x42
366 #define RF_BSPAD 0x54
367 #define RF_GAINTX 0x56
368 +#define RF_TXMOD 0x58
369 #define RF_TXATANK 0x64
370 +#define RF_TXA_PREPAD 0x65
371 #define RF_TRXIQ 0x66
372 #define RF_RXIQGEN 0x8d
373 +#define RF_RXBB2 0x8f
374 #define RF_SYN_PFD 0xb0
375 +#define RF_LCK 0xb4
376 #define RF_XTALX2 0xb8
377 #define RF_SYN_CTRL 0xbb
378 #define RF_MALSEL 0xbe
379 --- a/drivers/net/wireless/realtek/rtw88/rtw8821c.h
380 +++ b/drivers/net/wireless/realtek/rtw88/rtw8821c.h
381 @@ -214,19 +214,10 @@ extern const struct rtw_chip_info rtw882
382 #define BIT_FEN_EN BIT(26)
383 #define REG_INIRTS_RATE_SEL 0x0480
384 #define REG_HTSTFWT 0x800
385 -#define REG_RXPSEL 0x808
386 -#define BIT_RX_PSEL_RST (BIT(28) | BIT(29))
387 -#define REG_TXPSEL 0x80c
388 #define REG_RXCCAMSK 0x814
389 -#define REG_CCASEL 0x82c
390 -#define REG_PDMFTH 0x830
391 -#define REG_CCA2ND 0x838
392 #define REG_L1WT 0x83c
393 #define REG_L1PKWT 0x840
394 #define REG_MRC 0x850
395 -#define REG_CLKTRK 0x860
396 -#define REG_ADCCLK 0x8ac
397 -#define REG_ADC160 0x8c4
398 #define REG_ADC40 0x8c8
399 #define REG_CHFIR 0x8f0
400 #define REG_CDDTXP 0x93c
401 @@ -234,14 +225,11 @@ extern const struct rtw_chip_info rtw882
402 #define REG_ACBB0 0x948
403 #define REG_ACBBRXFIR 0x94c
404 #define REG_ACGG2TBL 0x958
405 -#define REG_FAS 0x9a4
406 -#define REG_RXSB 0xa00
407 #define REG_ADCINI 0xa04
408 #define REG_PWRTH 0xa08
409 #define REG_CCA_FLTR 0xa20
410 #define REG_TXSF2 0xa24
411 #define REG_TXSF6 0xa28
412 -#define REG_FA_CCK 0xa5c
413 #define REG_RXDESC 0xa2c
414 #define REG_ENTXCCK 0xa80
415 #define BTG_LNA 0xfc84
416 @@ -252,12 +240,8 @@ extern const struct rtw_chip_info rtw882
417 #define REG_PWRTH2 0xaa8
418 #define REG_CSRATIO 0xaaa
419 #define REG_TXFILTER 0xaac
420 -#define REG_CNTRST 0xb58
421 #define REG_AGCTR_A 0xc08
422 -#define REG_TXSCALE_A 0xc1c
423 #define REG_TXDFIR 0xc20
424 -#define REG_RXIGI_A 0xc50
425 -#define REG_TXAGCIDX 0xc94
426 #define REG_TRSW 0xca0
427 #define REG_RFESEL0 0xcb0
428 #define REG_RFESEL8 0xcb4
429 @@ -269,14 +253,6 @@ extern const struct rtw_chip_info rtw882
430 #define B_WLA_SWITCH BIT(23)
431 #define REG_RFEINV 0xcbc
432 #define REG_AGCTR_B 0xe08
433 -#define REG_RXIGI_B 0xe50
434 -#define REG_CRC_CCK 0xf04
435 -#define REG_CRC_OFDM 0xf14
436 -#define REG_CRC_HT 0xf10
437 -#define REG_CRC_VHT 0xf0c
438 -#define REG_CCA_OFDM 0xf08
439 -#define REG_FA_OFDM 0xf48
440 -#define REG_CCA_CCK 0xfcc
441 #define REG_DMEM_CTRL 0x1080
442 #define BIT_WL_RST BIT(16)
443 #define REG_ANTWT 0x1904
444 --- a/drivers/net/wireless/realtek/rtw88/rtw8822b.h
445 +++ b/drivers/net/wireless/realtek/rtw88/rtw8822b.h
446 @@ -151,21 +151,12 @@ _rtw_write32s_mask(struct rtw_dev *rtwde
447 #define RTW8822B_EDCCA_MAX 0x7f
448 #define RTW8822B_EDCCA_SRC_DEF 1
449 #define REG_HTSTFWT 0x800
450 -#define REG_RXPSEL 0x808
451 -#define BIT_RX_PSEL_RST (BIT(28) | BIT(29))
452 -#define REG_TXPSEL 0x80c
453 #define REG_RXCCAMSK 0x814
454 -#define REG_CCASEL 0x82c
455 -#define REG_PDMFTH 0x830
456 -#define REG_CCA2ND 0x838
457 #define REG_L1WT 0x83c
458 #define REG_L1PKWT 0x840
459 #define REG_MRC 0x850
460 -#define REG_CLKTRK 0x860
461 #define REG_EDCCA_POW_MA 0x8a0
462 #define BIT_MA_LEVEL GENMASK(1, 0)
463 -#define REG_ADCCLK 0x8ac
464 -#define REG_ADC160 0x8c4
465 #define REG_ADC40 0x8c8
466 #define REG_EDCCA_DECISION 0x8dc
467 #define BIT_EDCCA_OPTION BIT(5)
468 @@ -176,7 +167,6 @@ _rtw_write32s_mask(struct rtw_dev *rtwde
469 #define REG_ACBB0 0x948
470 #define REG_ACBBRXFIR 0x94c
471 #define REG_ACGG2TBL 0x958
472 -#define REG_RXSB 0xa00
473 #define REG_ADCINI 0xa04
474 #define REG_TXSF2 0xa24
475 #define REG_TXSF6 0xa28
476 @@ -184,14 +174,12 @@ _rtw_write32s_mask(struct rtw_dev *rtwde
477 #define REG_ENTXCCK 0xa80
478 #define REG_AGCTR_A 0xc08
479 #define REG_TXDFIR 0xc20
480 -#define REG_RXIGI_A 0xc50
481 #define REG_TRSW 0xca0
482 #define REG_RFESEL0 0xcb0
483 #define REG_RFESEL8 0xcb4
484 #define REG_RFECTL 0xcb8
485 #define REG_RFEINV 0xcbc
486 #define REG_AGCTR_B 0xe08
487 -#define REG_RXIGI_B 0xe50
488 #define REG_ANTWT 0x1904
489 #define REG_IQKFAILMSK 0x1bf0
490
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