git.openwrt.org Git - openwrt/staging/linusw.git/blob

   1 From 9e5e778f3340a687dd91c533064f963d352921c6 Mon Sep 17 00:00:00 2001
   2 From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
   3 Date: Sun, 20 Aug 2023 17:20:26 +0300
   4 Subject: [PATCH] arm64: dts: qcom: ipq8074: switch PCIe QMP PHY to new style
   5  of bindings
   6
   7 Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single
   8 resource region, no per-PHY subnodes).
   9
  10 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  11 Link: https://lore.kernel.org/r/20230820142035.89903-10-dmitry.baryshkov@linaro.org
  12 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  13 ---
  14  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 67 +++++++++++----------------
  15  1 file changed, 28 insertions(+), 39 deletions(-)
  16
  17 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  18 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  19 @@ -211,59 +211,48 @@
  20
  21                 pcie_qmp0: phy@84000 {
  22                         compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
  23 -                       reg = <0x00084000 0x1bc>;
  24 -                       #address-cells = <1>;
  25 -                       #size-cells = <1>;
  26 -                       ranges;
  27 +                       reg = <0x00084000 0x1000>;
  28
  29                         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
  30 -                               <&gcc GCC_PCIE0_AHB_CLK>;
  31 -                       clock-names = "aux", "cfg_ahb";
  32 +                                <&gcc GCC_PCIE0_AHB_CLK>,
  33 +                                <&gcc GCC_PCIE0_PIPE_CLK>;
  34 +                       clock-names = "aux",
  35 +                                     "cfg_ahb",
  36 +                                     "pipe";
  37 +
  38 +                       clock-output-names = "pcie20_phy0_pipe_clk";
  39 +                       #clock-cells = <0>;
  40 +
  41 +                       #phy-cells = <0>;
  42 +
  43                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
  44 -                               <&gcc GCC_PCIE0PHY_PHY_BCR>;
  45 +                                <&gcc GCC_PCIE0PHY_PHY_BCR>;
  46                         reset-names = "phy",
  47                                       "common";
  48                         status = "disabled";
  49 -
  50 -                       pcie_phy0: phy@84200 {
  51 -                               reg = <0x84200 0x16c>,
  52 -                                     <0x84400 0x200>,
  53 -                                     <0x84800 0x1f0>,
  54 -                                     <0x84c00 0xf4>;
  55 -                               #phy-cells = <0>;
  56 -                               #clock-cells = <0>;
  57 -                               clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
  58 -                               clock-names = "pipe0";
  59 -                               clock-output-names = "pcie20_phy0_pipe_clk";
  60 -                       };
  61                 };
  62
  63                 pcie_qmp1: phy@8e000 {
  64                         compatible = "qcom,ipq8074-qmp-pcie-phy";
  65 -                       reg = <0x0008e000 0x1c4>;
  66 -                       #address-cells = <1>;
  67 -                       #size-cells = <1>;
  68 -                       ranges;
  69 +                       reg = <0x0008e000 0x1000>;
  70
  71                         clocks = <&gcc GCC_PCIE1_AUX_CLK>,
  72 -                               <&gcc GCC_PCIE1_AHB_CLK>;
  73 -                       clock-names = "aux", "cfg_ahb";
  74 +                                <&gcc GCC_PCIE1_AHB_CLK>,
  75 +                                <&gcc GCC_PCIE1_PIPE_CLK>;
  76 +                       clock-names = "aux",
  77 +                                     "cfg_ahb",
  78 +                                     "pipe";
  79 +
  80 +                       clock-output-names = "pcie20_phy1_pipe_clk";
  81 +                       #clock-cells = <0>;
  82 +
  83 +                       #phy-cells = <0>;
  84 +
  85                         resets = <&gcc GCC_PCIE1_PHY_BCR>,
  86 -                               <&gcc GCC_PCIE1PHY_PHY_BCR>;
  87 +                                <&gcc GCC_PCIE1PHY_PHY_BCR>;
  88                         reset-names = "phy",
  89                                       "common";
  90                         status = "disabled";
  91 -
  92 -                       pcie_phy1: phy@8e200 {
  93 -                               reg = <0x8e200 0x130>,
  94 -                                     <0x8e400 0x200>,
  95 -                                     <0x8e800 0x1f8>;
  96 -                               #phy-cells = <0>;
  97 -                               #clock-cells = <0>;
  98 -                               clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
  99 -                               clock-names = "pipe0";
 100 -                               clock-output-names = "pcie20_phy1_pipe_clk";
 101 -                       };
 102                 };
 103
 104                 mdio: mdio@90000 {
 105 @@ -839,7 +828,7 @@
 106                         #address-cells = <3>;
 107                         #size-cells = <2>;
 108
 109 -                       phys = <&pcie_phy1>;
 110 +                       phys = <&pcie_qmp1>;
 111                         phy-names = "pciephy";
 112
 113                         ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
 114 @@ -901,7 +890,7 @@
 115                         #address-cells = <3>;
 116                         #size-cells = <2>;
 117
 118 -                       phys = <&pcie_phy0>;
 119 +                       phys = <&pcie_qmp0>;
 120                         phy-names = "pciephy";
 121
 122                         ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */