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1 From 4043b0c45f8555a079bdac69a19ed08695a47a7b Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Fri, 7 Nov 2025 00:57:04 +0100
4 Subject: [PATCH 1/5] pinctrl: airoha: generalize pins/group/function/confs
5 handling
6
7 In preparation for support of Airoha AN7583, generalize
8 pins/group/function/confs handling and move them in match_data.
9 Inner function will base the values on the pinctrl priv struct instead of
10 relying on hardcoded struct.
11
12 This permits to use different PIN data while keeping the same logic.
13
14 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
15 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
16 ---
17 drivers/pinctrl/mediatek/pinctrl-airoha.c | 567 ++++++++++++----------
18 1 file changed, 318 insertions(+), 249 deletions(-)
19
20 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
21 +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
22 @@ -30,20 +30,20 @@
23 #include "../pinconf.h"
24 #include "../pinmux.h"
25
26 -#define PINCTRL_PIN_GROUP(id) \
27 - PINCTRL_PINGROUP(#id, id##_pins, ARRAY_SIZE(id##_pins))
28 +#define PINCTRL_PIN_GROUP(id, table) \
29 + PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
30
31 -#define PINCTRL_FUNC_DESC(id) \
32 +#define PINCTRL_FUNC_DESC(id, table) \
33 { \
34 .desc = { \
35 .func = { \
36 .name = #id, \
37 - .groups = id##_groups, \
38 - .ngroups = ARRAY_SIZE(id##_groups), \
39 + .groups = table##_groups, \
40 + .ngroups = ARRAY_SIZE(table##_groups), \
41 } \
42 }, \
43 - .groups = id##_func_group, \
44 - .group_size = ARRAY_SIZE(id##_func_group), \
45 + .groups = table##_func_group, \
46 + .group_size = ARRAY_SIZE(table##_func_group), \
47 }
48
49 #define PINCTRL_CONF_DESC(p, offset, mask) \
50 @@ -362,16 +362,46 @@ struct airoha_pinctrl_gpiochip {
51 u32 irq_type[AIROHA_NUM_PINS];
52 };
53
54 +struct airoha_pinctrl_confs_info {
55 + const struct airoha_pinctrl_conf *confs;
56 + unsigned int num_confs;
57 +};
58 +
59 +enum airoha_pinctrl_confs_type {
60 + AIROHA_PINCTRL_CONFS_PULLUP,
61 + AIROHA_PINCTRL_CONFS_PULLDOWN,
62 + AIROHA_PINCTRL_CONFS_DRIVE_E2,
63 + AIROHA_PINCTRL_CONFS_DRIVE_E4,
64 + AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
65 +
66 + AIROHA_PINCTRL_CONFS_MAX,
67 +};
68 +
69 struct airoha_pinctrl {
70 struct pinctrl_dev *ctrl;
71
72 + struct pinctrl_desc desc;
73 + const struct pingroup *grps;
74 + const struct airoha_pinctrl_func *funcs;
75 + const struct airoha_pinctrl_confs_info *confs_info;
76 +
77 struct regmap *chip_scu;
78 struct regmap *regmap;
79
80 struct airoha_pinctrl_gpiochip gpiochip;
81 };
82
83 -static struct pinctrl_pin_desc airoha_pinctrl_pins[] = {
84 +struct airoha_pinctrl_match_data {
85 + const struct pinctrl_pin_desc *pins;
86 + const unsigned int num_pins;
87 + const struct pingroup *grps;
88 + const unsigned int num_grps;
89 + const struct airoha_pinctrl_func *funcs;
90 + const unsigned int num_funcs;
91 + const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
92 +};
93 +
94 +static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
95 PINCTRL_PIN(0, "uart1_txd"),
96 PINCTRL_PIN(1, "uart1_rxd"),
97 PINCTRL_PIN(2, "i2c_scl"),
98 @@ -432,172 +462,172 @@ static struct pinctrl_pin_desc airoha_pi
99 PINCTRL_PIN(63, "pcie_reset2"),
100 };
101
102 -static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
103 -static const int pon_tod_1pps_pins[] = { 46 };
104 -static const int gsw_tod_1pps_pins[] = { 46 };
105 -static const int sipo_pins[] = { 16, 17 };
106 -static const int sipo_rclk_pins[] = { 16, 17, 43 };
107 -static const int mdio_pins[] = { 14, 15 };
108 -static const int uart2_pins[] = { 48, 55 };
109 -static const int uart2_cts_rts_pins[] = { 46, 47 };
110 -static const int hsuart_pins[] = { 28, 29 };
111 -static const int hsuart_cts_rts_pins[] = { 26, 27 };
112 -static const int uart4_pins[] = { 38, 39 };
113 -static const int uart5_pins[] = { 18, 19 };
114 -static const int i2c0_pins[] = { 2, 3 };
115 -static const int i2c1_pins[] = { 14, 15 };
116 -static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
117 -static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
118 -static const int i2s_pins[] = { 26, 27, 28, 29 };
119 -static const int pcm1_pins[] = { 22, 23, 24, 25 };
120 -static const int pcm2_pins[] = { 18, 19, 20, 21 };
121 -static const int spi_quad_pins[] = { 32, 33 };
122 -static const int spi_pins[] = { 4, 5, 6, 7 };
123 -static const int spi_cs1_pins[] = { 34 };
124 -static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
125 -static const int pcm_spi_int_pins[] = { 14 };
126 -static const int pcm_spi_rst_pins[] = { 15 };
127 -static const int pcm_spi_cs1_pins[] = { 43 };
128 -static const int pcm_spi_cs2_pins[] = { 40 };
129 -static const int pcm_spi_cs2_p128_pins[] = { 40 };
130 -static const int pcm_spi_cs2_p156_pins[] = { 40 };
131 -static const int pcm_spi_cs3_pins[] = { 41 };
132 -static const int pcm_spi_cs4_pins[] = { 42 };
133 -static const int emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
134 -static const int pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
135 -static const int gpio0_pins[] = { 13 };
136 -static const int gpio1_pins[] = { 14 };
137 -static const int gpio2_pins[] = { 15 };
138 -static const int gpio3_pins[] = { 16 };
139 -static const int gpio4_pins[] = { 17 };
140 -static const int gpio5_pins[] = { 18 };
141 -static const int gpio6_pins[] = { 19 };
142 -static const int gpio7_pins[] = { 20 };
143 -static const int gpio8_pins[] = { 21 };
144 -static const int gpio9_pins[] = { 22 };
145 -static const int gpio10_pins[] = { 23 };
146 -static const int gpio11_pins[] = { 24 };
147 -static const int gpio12_pins[] = { 25 };
148 -static const int gpio13_pins[] = { 26 };
149 -static const int gpio14_pins[] = { 27 };
150 -static const int gpio15_pins[] = { 28 };
151 -static const int gpio16_pins[] = { 29 };
152 -static const int gpio17_pins[] = { 30 };
153 -static const int gpio18_pins[] = { 31 };
154 -static const int gpio19_pins[] = { 32 };
155 -static const int gpio20_pins[] = { 33 };
156 -static const int gpio21_pins[] = { 34 };
157 -static const int gpio22_pins[] = { 35 };
158 -static const int gpio23_pins[] = { 36 };
159 -static const int gpio24_pins[] = { 37 };
160 -static const int gpio25_pins[] = { 38 };
161 -static const int gpio26_pins[] = { 39 };
162 -static const int gpio27_pins[] = { 40 };
163 -static const int gpio28_pins[] = { 41 };
164 -static const int gpio29_pins[] = { 42 };
165 -static const int gpio30_pins[] = { 43 };
166 -static const int gpio31_pins[] = { 44 };
167 -static const int gpio33_pins[] = { 46 };
168 -static const int gpio34_pins[] = { 47 };
169 -static const int gpio35_pins[] = { 48 };
170 -static const int gpio36_pins[] = { 49 };
171 -static const int gpio37_pins[] = { 50 };
172 -static const int gpio38_pins[] = { 51 };
173 -static const int gpio39_pins[] = { 52 };
174 -static const int gpio40_pins[] = { 53 };
175 -static const int gpio41_pins[] = { 54 };
176 -static const int gpio42_pins[] = { 55 };
177 -static const int gpio43_pins[] = { 56 };
178 -static const int gpio44_pins[] = { 57 };
179 -static const int gpio45_pins[] = { 58 };
180 -static const int gpio46_pins[] = { 59 };
181 -static const int pcie_reset0_pins[] = { 61 };
182 -static const int pcie_reset1_pins[] = { 62 };
183 -static const int pcie_reset2_pins[] = { 63 };
184 -
185 -static const struct pingroup airoha_pinctrl_groups[] = {
186 - PINCTRL_PIN_GROUP(pon),
187 - PINCTRL_PIN_GROUP(pon_tod_1pps),
188 - PINCTRL_PIN_GROUP(gsw_tod_1pps),
189 - PINCTRL_PIN_GROUP(sipo),
190 - PINCTRL_PIN_GROUP(sipo_rclk),
191 - PINCTRL_PIN_GROUP(mdio),
192 - PINCTRL_PIN_GROUP(uart2),
193 - PINCTRL_PIN_GROUP(uart2_cts_rts),
194 - PINCTRL_PIN_GROUP(hsuart),
195 - PINCTRL_PIN_GROUP(hsuart_cts_rts),
196 - PINCTRL_PIN_GROUP(uart4),
197 - PINCTRL_PIN_GROUP(uart5),
198 - PINCTRL_PIN_GROUP(i2c0),
199 - PINCTRL_PIN_GROUP(i2c1),
200 - PINCTRL_PIN_GROUP(jtag_udi),
201 - PINCTRL_PIN_GROUP(jtag_dfd),
202 - PINCTRL_PIN_GROUP(i2s),
203 - PINCTRL_PIN_GROUP(pcm1),
204 - PINCTRL_PIN_GROUP(pcm2),
205 - PINCTRL_PIN_GROUP(spi),
206 - PINCTRL_PIN_GROUP(spi_quad),
207 - PINCTRL_PIN_GROUP(spi_cs1),
208 - PINCTRL_PIN_GROUP(pcm_spi),
209 - PINCTRL_PIN_GROUP(pcm_spi_int),
210 - PINCTRL_PIN_GROUP(pcm_spi_rst),
211 - PINCTRL_PIN_GROUP(pcm_spi_cs1),
212 - PINCTRL_PIN_GROUP(pcm_spi_cs2_p128),
213 - PINCTRL_PIN_GROUP(pcm_spi_cs2_p156),
214 - PINCTRL_PIN_GROUP(pcm_spi_cs2),
215 - PINCTRL_PIN_GROUP(pcm_spi_cs3),
216 - PINCTRL_PIN_GROUP(pcm_spi_cs4),
217 - PINCTRL_PIN_GROUP(emmc),
218 - PINCTRL_PIN_GROUP(pnand),
219 - PINCTRL_PIN_GROUP(gpio0),
220 - PINCTRL_PIN_GROUP(gpio1),
221 - PINCTRL_PIN_GROUP(gpio2),
222 - PINCTRL_PIN_GROUP(gpio3),
223 - PINCTRL_PIN_GROUP(gpio4),
224 - PINCTRL_PIN_GROUP(gpio5),
225 - PINCTRL_PIN_GROUP(gpio6),
226 - PINCTRL_PIN_GROUP(gpio7),
227 - PINCTRL_PIN_GROUP(gpio8),
228 - PINCTRL_PIN_GROUP(gpio9),
229 - PINCTRL_PIN_GROUP(gpio10),
230 - PINCTRL_PIN_GROUP(gpio11),
231 - PINCTRL_PIN_GROUP(gpio12),
232 - PINCTRL_PIN_GROUP(gpio13),
233 - PINCTRL_PIN_GROUP(gpio14),
234 - PINCTRL_PIN_GROUP(gpio15),
235 - PINCTRL_PIN_GROUP(gpio16),
236 - PINCTRL_PIN_GROUP(gpio17),
237 - PINCTRL_PIN_GROUP(gpio18),
238 - PINCTRL_PIN_GROUP(gpio19),
239 - PINCTRL_PIN_GROUP(gpio20),
240 - PINCTRL_PIN_GROUP(gpio21),
241 - PINCTRL_PIN_GROUP(gpio22),
242 - PINCTRL_PIN_GROUP(gpio23),
243 - PINCTRL_PIN_GROUP(gpio24),
244 - PINCTRL_PIN_GROUP(gpio25),
245 - PINCTRL_PIN_GROUP(gpio26),
246 - PINCTRL_PIN_GROUP(gpio27),
247 - PINCTRL_PIN_GROUP(gpio28),
248 - PINCTRL_PIN_GROUP(gpio29),
249 - PINCTRL_PIN_GROUP(gpio30),
250 - PINCTRL_PIN_GROUP(gpio31),
251 - PINCTRL_PIN_GROUP(gpio33),
252 - PINCTRL_PIN_GROUP(gpio34),
253 - PINCTRL_PIN_GROUP(gpio35),
254 - PINCTRL_PIN_GROUP(gpio36),
255 - PINCTRL_PIN_GROUP(gpio37),
256 - PINCTRL_PIN_GROUP(gpio38),
257 - PINCTRL_PIN_GROUP(gpio39),
258 - PINCTRL_PIN_GROUP(gpio40),
259 - PINCTRL_PIN_GROUP(gpio41),
260 - PINCTRL_PIN_GROUP(gpio42),
261 - PINCTRL_PIN_GROUP(gpio43),
262 - PINCTRL_PIN_GROUP(gpio44),
263 - PINCTRL_PIN_GROUP(gpio45),
264 - PINCTRL_PIN_GROUP(gpio46),
265 - PINCTRL_PIN_GROUP(pcie_reset0),
266 - PINCTRL_PIN_GROUP(pcie_reset1),
267 - PINCTRL_PIN_GROUP(pcie_reset2),
268 +static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
269 +static const int en7581_pon_tod_1pps_pins[] = { 46 };
270 +static const int en7581_gsw_tod_1pps_pins[] = { 46 };
271 +static const int en7581_sipo_pins[] = { 16, 17 };
272 +static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
273 +static const int en7581_mdio_pins[] = { 14, 15 };
274 +static const int en7581_uart2_pins[] = { 48, 55 };
275 +static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
276 +static const int en7581_hsuart_pins[] = { 28, 29 };
277 +static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
278 +static const int en7581_uart4_pins[] = { 38, 39 };
279 +static const int en7581_uart5_pins[] = { 18, 19 };
280 +static const int en7581_i2c0_pins[] = { 2, 3 };
281 +static const int en7581_i2c1_pins[] = { 14, 15 };
282 +static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
283 +static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
284 +static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
285 +static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
286 +static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
287 +static const int en7581_spi_quad_pins[] = { 32, 33 };
288 +static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
289 +static const int en7581_spi_cs1_pins[] = { 34 };
290 +static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
291 +static const int en7581_pcm_spi_int_pins[] = { 14 };
292 +static const int en7581_pcm_spi_rst_pins[] = { 15 };
293 +static const int en7581_pcm_spi_cs1_pins[] = { 43 };
294 +static const int en7581_pcm_spi_cs2_pins[] = { 40 };
295 +static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
296 +static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
297 +static const int en7581_pcm_spi_cs3_pins[] = { 41 };
298 +static const int en7581_pcm_spi_cs4_pins[] = { 42 };
299 +static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
300 +static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
301 +static const int en7581_gpio0_pins[] = { 13 };
302 +static const int en7581_gpio1_pins[] = { 14 };
303 +static const int en7581_gpio2_pins[] = { 15 };
304 +static const int en7581_gpio3_pins[] = { 16 };
305 +static const int en7581_gpio4_pins[] = { 17 };
306 +static const int en7581_gpio5_pins[] = { 18 };
307 +static const int en7581_gpio6_pins[] = { 19 };
308 +static const int en7581_gpio7_pins[] = { 20 };
309 +static const int en7581_gpio8_pins[] = { 21 };
310 +static const int en7581_gpio9_pins[] = { 22 };
311 +static const int en7581_gpio10_pins[] = { 23 };
312 +static const int en7581_gpio11_pins[] = { 24 };
313 +static const int en7581_gpio12_pins[] = { 25 };
314 +static const int en7581_gpio13_pins[] = { 26 };
315 +static const int en7581_gpio14_pins[] = { 27 };
316 +static const int en7581_gpio15_pins[] = { 28 };
317 +static const int en7581_gpio16_pins[] = { 29 };
318 +static const int en7581_gpio17_pins[] = { 30 };
319 +static const int en7581_gpio18_pins[] = { 31 };
320 +static const int en7581_gpio19_pins[] = { 32 };
321 +static const int en7581_gpio20_pins[] = { 33 };
322 +static const int en7581_gpio21_pins[] = { 34 };
323 +static const int en7581_gpio22_pins[] = { 35 };
324 +static const int en7581_gpio23_pins[] = { 36 };
325 +static const int en7581_gpio24_pins[] = { 37 };
326 +static const int en7581_gpio25_pins[] = { 38 };
327 +static const int en7581_gpio26_pins[] = { 39 };
328 +static const int en7581_gpio27_pins[] = { 40 };
329 +static const int en7581_gpio28_pins[] = { 41 };
330 +static const int en7581_gpio29_pins[] = { 42 };
331 +static const int en7581_gpio30_pins[] = { 43 };
332 +static const int en7581_gpio31_pins[] = { 44 };
333 +static const int en7581_gpio33_pins[] = { 46 };
334 +static const int en7581_gpio34_pins[] = { 47 };
335 +static const int en7581_gpio35_pins[] = { 48 };
336 +static const int en7581_gpio36_pins[] = { 49 };
337 +static const int en7581_gpio37_pins[] = { 50 };
338 +static const int en7581_gpio38_pins[] = { 51 };
339 +static const int en7581_gpio39_pins[] = { 52 };
340 +static const int en7581_gpio40_pins[] = { 53 };
341 +static const int en7581_gpio41_pins[] = { 54 };
342 +static const int en7581_gpio42_pins[] = { 55 };
343 +static const int en7581_gpio43_pins[] = { 56 };
344 +static const int en7581_gpio44_pins[] = { 57 };
345 +static const int en7581_gpio45_pins[] = { 58 };
346 +static const int en7581_gpio46_pins[] = { 59 };
347 +static const int en7581_pcie_reset0_pins[] = { 61 };
348 +static const int en7581_pcie_reset1_pins[] = { 62 };
349 +static const int en7581_pcie_reset2_pins[] = { 63 };
350 +
351 +static const struct pingroup en7581_pinctrl_groups[] = {
352 + PINCTRL_PIN_GROUP("pon", en7581_pon),
353 + PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
354 + PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
355 + PINCTRL_PIN_GROUP("sipo", en7581_sipo),
356 + PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
357 + PINCTRL_PIN_GROUP("mdio", en7581_mdio),
358 + PINCTRL_PIN_GROUP("uart2", en7581_uart2),
359 + PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
360 + PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
361 + PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
362 + PINCTRL_PIN_GROUP("uart4", en7581_uart4),
363 + PINCTRL_PIN_GROUP("uart5", en7581_uart5),
364 + PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
365 + PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
366 + PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
367 + PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
368 + PINCTRL_PIN_GROUP("i2s", en7581_i2s),
369 + PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
370 + PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
371 + PINCTRL_PIN_GROUP("spi", en7581_spi),
372 + PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
373 + PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
374 + PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
375 + PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
376 + PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
377 + PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
378 + PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
379 + PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
380 + PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
381 + PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
382 + PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
383 + PINCTRL_PIN_GROUP("emmc", en7581_emmc),
384 + PINCTRL_PIN_GROUP("pnand", en7581_pnand),
385 + PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
386 + PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
387 + PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
388 + PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
389 + PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
390 + PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
391 + PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
392 + PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
393 + PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
394 + PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
395 + PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
396 + PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
397 + PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
398 + PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
399 + PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
400 + PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
401 + PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
402 + PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
403 + PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
404 + PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
405 + PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
406 + PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
407 + PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
408 + PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
409 + PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
410 + PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
411 + PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
412 + PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
413 + PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
414 + PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
415 + PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
416 + PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
417 + PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
418 + PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
419 + PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
420 + PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
421 + PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
422 + PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
423 + PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
424 + PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
425 + PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
426 + PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
427 + PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
428 + PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
429 + PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
430 + PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
431 + PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
432 + PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
433 + PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
434 };
435
436 static const char *const pon_groups[] = { "pon" };
437 @@ -1960,33 +1990,33 @@ static const struct airoha_pinctrl_func_
438 },
439 };
440
441 -static const struct airoha_pinctrl_func airoha_pinctrl_funcs[] = {
442 - PINCTRL_FUNC_DESC(pon),
443 - PINCTRL_FUNC_DESC(tod_1pps),
444 - PINCTRL_FUNC_DESC(sipo),
445 - PINCTRL_FUNC_DESC(mdio),
446 - PINCTRL_FUNC_DESC(uart),
447 - PINCTRL_FUNC_DESC(i2c),
448 - PINCTRL_FUNC_DESC(jtag),
449 - PINCTRL_FUNC_DESC(pcm),
450 - PINCTRL_FUNC_DESC(spi),
451 - PINCTRL_FUNC_DESC(pcm_spi),
452 - PINCTRL_FUNC_DESC(i2s),
453 - PINCTRL_FUNC_DESC(emmc),
454 - PINCTRL_FUNC_DESC(pnand),
455 - PINCTRL_FUNC_DESC(pcie_reset),
456 - PINCTRL_FUNC_DESC(pwm),
457 - PINCTRL_FUNC_DESC(phy1_led0),
458 - PINCTRL_FUNC_DESC(phy2_led0),
459 - PINCTRL_FUNC_DESC(phy3_led0),
460 - PINCTRL_FUNC_DESC(phy4_led0),
461 - PINCTRL_FUNC_DESC(phy1_led1),
462 - PINCTRL_FUNC_DESC(phy2_led1),
463 - PINCTRL_FUNC_DESC(phy3_led1),
464 - PINCTRL_FUNC_DESC(phy4_led1),
465 +static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
466 + PINCTRL_FUNC_DESC("pon", pon),
467 + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
468 + PINCTRL_FUNC_DESC("sipo", sipo),
469 + PINCTRL_FUNC_DESC("mdio", mdio),
470 + PINCTRL_FUNC_DESC("uart", uart),
471 + PINCTRL_FUNC_DESC("i2c", i2c),
472 + PINCTRL_FUNC_DESC("jtag", jtag),
473 + PINCTRL_FUNC_DESC("pcm", pcm),
474 + PINCTRL_FUNC_DESC("spi", spi),
475 + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
476 + PINCTRL_FUNC_DESC("i2s", i2s),
477 + PINCTRL_FUNC_DESC("emmc", emmc),
478 + PINCTRL_FUNC_DESC("pnand", pnand),
479 + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
480 + PINCTRL_FUNC_DESC("pwm", pwm),
481 + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
482 + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
483 + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
484 + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
485 + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
486 + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
487 + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
488 + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
489 };
490
491 -static const struct airoha_pinctrl_conf airoha_pinctrl_pullup_conf[] = {
492 +static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
493 PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
494 PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
495 PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
496 @@ -2047,7 +2077,7 @@ static const struct airoha_pinctrl_conf
497 PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
498 };
499
500 -static const struct airoha_pinctrl_conf airoha_pinctrl_pulldown_conf[] = {
501 +static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
502 PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
503 PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
504 PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
505 @@ -2108,7 +2138,7 @@ static const struct airoha_pinctrl_conf
506 PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
507 };
508
509 -static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e2_conf[] = {
510 +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
511 PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
512 PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
513 PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
514 @@ -2169,7 +2199,7 @@ static const struct airoha_pinctrl_conf
515 PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
516 };
517
518 -static const struct airoha_pinctrl_conf airoha_pinctrl_drive_e4_conf[] = {
519 +static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
520 PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
521 PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
522 PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
523 @@ -2230,7 +2260,7 @@ static const struct airoha_pinctrl_conf
524 PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
525 };
526
527 -static const struct airoha_pinctrl_conf airoha_pinctrl_pcie_rst_od_conf[] = {
528 +static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
529 PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
530 PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
531 PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
532 @@ -2552,12 +2582,17 @@ airoha_pinctrl_get_conf_reg(const struct
533 }
534
535 static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl,
536 - const struct airoha_pinctrl_conf *conf,
537 - int conf_size, int pin, u32 *val)
538 + enum airoha_pinctrl_confs_type conf_type,
539 + int pin, u32 *val)
540 {
541 + const struct airoha_pinctrl_confs_info *confs_info;
542 const struct airoha_pinctrl_reg *reg;
543
544 - reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
545 + confs_info = &pinctrl->confs_info[conf_type];
546 +
547 + reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
548 + confs_info->num_confs,
549 + pin);
550 if (!reg)
551 return -EINVAL;
552
553 @@ -2570,12 +2605,17 @@ static int airoha_pinctrl_get_conf(struc
554 }
555
556 static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl,
557 - const struct airoha_pinctrl_conf *conf,
558 - int conf_size, int pin, u32 val)
559 + enum airoha_pinctrl_confs_type conf_type,
560 + int pin, u32 val)
561 {
562 + const struct airoha_pinctrl_confs_info *confs_info;
563 const struct airoha_pinctrl_reg *reg = NULL;
564
565 - reg = airoha_pinctrl_get_conf_reg(conf, conf_size, pin);
566 + confs_info = &pinctrl->confs_info[conf_type];
567 +
568 + reg = airoha_pinctrl_get_conf_reg(confs_info->confs,
569 + confs_info->num_confs,
570 + pin);
571 if (!reg)
572 return -EINVAL;
573
574 @@ -2588,44 +2628,34 @@ static int airoha_pinctrl_set_conf(struc
575 }
576
577 #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \
578 - airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pullup_conf, \
579 - ARRAY_SIZE(airoha_pinctrl_pullup_conf), \
580 + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
581 (pin), (val))
582 #define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \
583 - airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pulldown_conf, \
584 - ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \
585 + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
586 (pin), (val))
587 #define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \
588 - airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \
589 - ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \
590 + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
591 (pin), (val))
592 #define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \
593 - airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \
594 - ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \
595 + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
596 (pin), (val))
597 #define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \
598 - airoha_pinctrl_get_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \
599 - ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \
600 + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
601 (pin), (val))
602 #define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \
603 - airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pullup_conf, \
604 - ARRAY_SIZE(airoha_pinctrl_pullup_conf), \
605 + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \
606 (pin), (val))
607 #define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \
608 - airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pulldown_conf, \
609 - ARRAY_SIZE(airoha_pinctrl_pulldown_conf), \
610 + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \
611 (pin), (val))
612 #define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \
613 - airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e2_conf, \
614 - ARRAY_SIZE(airoha_pinctrl_drive_e2_conf), \
615 + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \
616 (pin), (val))
617 #define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \
618 - airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_drive_e4_conf, \
619 - ARRAY_SIZE(airoha_pinctrl_drive_e4_conf), \
620 + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \
621 (pin), (val))
622 #define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \
623 - airoha_pinctrl_set_conf((pinctrl), airoha_pinctrl_pcie_rst_od_conf, \
624 - ARRAY_SIZE(airoha_pinctrl_pcie_rst_od_conf), \
625 + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \
626 (pin), (val))
627
628 static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
629 @@ -2804,12 +2834,13 @@ static int airoha_pinconf_set(struct pin
630 static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev,
631 unsigned int group, unsigned long *config)
632 {
633 + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
634 u32 cur_config = 0;
635 int i;
636
637 - for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
638 + for (i = 0; i < pinctrl->grps[group].npins; i++) {
639 if (airoha_pinconf_get(pctrl_dev,
640 - airoha_pinctrl_groups[group].pins[i],
641 + pinctrl->grps[group].pins[i],
642 config))
643 return -ENOTSUPP;
644
645 @@ -2826,13 +2857,14 @@ static int airoha_pinconf_group_set(stru
646 unsigned int group, unsigned long *configs,
647 unsigned int num_configs)
648 {
649 + struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
650 int i;
651
652 - for (i = 0; i < airoha_pinctrl_groups[group].npins; i++) {
653 + for (i = 0; i < pinctrl->grps[group].npins; i++) {
654 int err;
655
656 err = airoha_pinconf_set(pctrl_dev,
657 - airoha_pinctrl_groups[group].pins[i],
658 + pinctrl->grps[group].pins[i],
659 configs, num_configs);
660 if (err)
661 return err;
662 @@ -2858,23 +2890,16 @@ static const struct pinctrl_ops airoha_p
663 .dt_free_map = pinconf_generic_dt_free_map,
664 };
665
666 -static struct pinctrl_desc airoha_pinctrl_desc = {
667 - .name = KBUILD_MODNAME,
668 - .owner = THIS_MODULE,
669 - .pctlops = &airoha_pctlops,
670 - .pmxops = &airoha_pmxops,
671 - .confops = &airoha_confops,
672 - .pins = airoha_pinctrl_pins,
673 - .npins = ARRAY_SIZE(airoha_pinctrl_pins),
674 -};
675 -
676 static int airoha_pinctrl_probe(struct platform_device *pdev)
677 {
678 + const struct airoha_pinctrl_match_data *data;
679 struct device *dev = &pdev->dev;
680 struct airoha_pinctrl *pinctrl;
681 struct regmap *map;
682 int err, i;
683
684 + data = device_get_match_data(dev);
685 +
686 pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
687 if (!pinctrl)
688 return -ENOMEM;
689 @@ -2889,14 +2914,23 @@ static int airoha_pinctrl_probe(struct p
690
691 pinctrl->chip_scu = map;
692
693 - err = devm_pinctrl_register_and_init(dev, &airoha_pinctrl_desc,
694 + /* Init pinctrl desc struct */
695 + pinctrl->desc.name = KBUILD_MODNAME;
696 + pinctrl->desc.owner = THIS_MODULE,
697 + pinctrl->desc.pctlops = &airoha_pctlops,
698 + pinctrl->desc.pmxops = &airoha_pmxops,
699 + pinctrl->desc.confops = &airoha_confops,
700 + pinctrl->desc.pins = data->pins,
701 + pinctrl->desc.npins = data->num_pins,
702 +
703 + err = devm_pinctrl_register_and_init(dev, &pinctrl->desc,
704 pinctrl, &pinctrl->ctrl);
705 if (err)
706 return err;
707
708 /* build pin groups */
709 - for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_groups); i++) {
710 - const struct pingroup *grp = &airoha_pinctrl_groups[i];
711 + for (i = 0; i < data->num_grps; i++) {
712 + const struct pingroup *grp = &data->grps[i];
713
714 err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name,
715 grp->pins, grp->npins,
716 @@ -2909,10 +2943,10 @@ static int airoha_pinctrl_probe(struct p
717 }
718
719 /* build functions */
720 - for (i = 0; i < ARRAY_SIZE(airoha_pinctrl_funcs); i++) {
721 + for (i = 0; i < data->num_funcs; i++) {
722 const struct airoha_pinctrl_func *func;
723
724 - func = &airoha_pinctrl_funcs[i];
725 + func = &data->funcs[i];
726 err = pinmux_generic_add_function(pinctrl->ctrl,
727 func->desc.func.name,
728 func->desc.func.groups,
729 @@ -2925,6 +2959,10 @@ static int airoha_pinctrl_probe(struct p
730 }
731 }
732
733 + pinctrl->grps = data->grps;
734 + pinctrl->funcs = data->funcs;
735 + pinctrl->confs_info = data->confs_info;
736 +
737 err = pinctrl_enable(pinctrl->ctrl);
738 if (err)
739 return err;
740 @@ -2933,8 +2971,39 @@ static int airoha_pinctrl_probe(struct p
741 return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
742 }
743
744 +static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
745 + .pins = en7581_pinctrl_pins,
746 + .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
747 + .grps = en7581_pinctrl_groups,
748 + .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
749 + .funcs = en7581_pinctrl_funcs,
750 + .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
751 + .confs_info = {
752 + [AIROHA_PINCTRL_CONFS_PULLUP] = {
753 + .confs = en7581_pinctrl_pullup_conf,
754 + .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
755 + },
756 + [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
757 + .confs = en7581_pinctrl_pulldown_conf,
758 + .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
759 + },
760 + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
761 + .confs = en7581_pinctrl_drive_e2_conf,
762 + .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
763 + },
764 + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
765 + .confs = en7581_pinctrl_drive_e4_conf,
766 + .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
767 + },
768 + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
769 + .confs = en7581_pinctrl_pcie_rst_od_conf,
770 + .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
771 + },
772 + },
773 +};
774 +
775 static const struct of_device_id airoha_pinctrl_of_match[] = {
776 - { .compatible = "airoha,en7581-pinctrl" },
777 + { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
778 { /* sentinel */ }
779 };
780 MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
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