git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 930203b9bb94dc4ea9342f1ce176851918758ed7 Mon Sep 17 00:00:00 2001
   2 From: Mantas Pucka <mantas@8devices.com>
   3 Date: Mon, 2 Jun 2025 17:18:13 +0300
   4 Subject: [PATCH] net: pcs: ipq-uniphy: control MISC2 register for 2.5G
   5  support
   6
   7 When 2500base-x mode is enabled MISC2 regsister needs to have different
   8 value than for other 1G modes.
   9
  10 Signed-off-by: Mantas Pucka <mantas@8devices.com>
  11 ---
  12  drivers/net/pcs/pcs-qcom-ipq9574.c | 17 ++++++++++++++++-
  13  1 file changed, 16 insertions(+), 1 deletion(-)
  14
  15 --- a/drivers/net/pcs/pcs-qcom-ipq9574.c
  16 +++ b/drivers/net/pcs/pcs-qcom-ipq9574.c
  17 @@ -24,6 +24,11 @@
  18  #define PCS_CALIBRATION                        0x1e0
  19  #define PCS_CALIBRATION_DONE           BIT(7)
  20
  21 +#define PCS_MISC2                      0x218
  22 +#define PCS_MISC2_MODE_MASK            GENMASK(6, 5)
  23 +#define PCS_MISC2_MODE_SGMII           FIELD_PREP(PCS_MISC2_MODE_MASK, 0x1)
  24 +#define PCS_MISC2_MODE_SGMII_PLUS      FIELD_PREP(PCS_MISC2_MODE_MASK, 0x2)
  25 +
  26  #define PCS_MODE_CTRL                  0x46c
  27  #define PCS_MODE_SEL_MASK              GENMASK(12, 8)
  28  #define PCS_MODE_SGMII                 FIELD_PREP(PCS_MODE_SEL_MASK, 0x4)
  29 @@ -311,7 +316,7 @@ static int ipq_pcs_config_mode(struct ip
  30                                phy_interface_t interface)
  31  {
  32         unsigned long rate = 125000000;
  33 -       unsigned int val, mask = PCS_MODE_SEL_MASK;
  34 +       unsigned int val, misc2 = 0, mask = PCS_MODE_SEL_MASK;
  35         int ret;
  36
  37         /* Assert XPCS reset */
  38 @@ -321,6 +326,7 @@ static int ipq_pcs_config_mode(struct ip
  39         switch (interface) {
  40         case PHY_INTERFACE_MODE_SGMII:
  41                 val = PCS_MODE_SGMII;
  42 +               misc2 = PCS_MISC2_MODE_SGMII;
  43                 break;
  44         case PHY_INTERFACE_MODE_QSGMII:
  45                 val = PCS_MODE_QSGMII;
  46 @@ -328,10 +334,12 @@ static int ipq_pcs_config_mode(struct ip
  47         case PHY_INTERFACE_MODE_1000BASEX:
  48                 mask |= PCS_MODE_SGMII_CTRL_MASK;
  49                 val = PCS_MODE_SGMII | PCS_MODE_SGMII_CTRL_1000BASEX;
  50 +               misc2 = PCS_MISC2_MODE_SGMII;
  51                 break;
  52         case PHY_INTERFACE_MODE_2500BASEX:
  53                 val = PCS_MODE_SGMII_PLUS;
  54                 rate = 312500000;
  55 +               misc2 = PCS_MISC2_MODE_SGMII_PLUS;
  56                 break;
  57         case PHY_INTERFACE_MODE_PSGMII:
  58                 val = PCS_MODE_PSGMII;
  59 @@ -360,6 +368,13 @@ static int ipq_pcs_config_mode(struct ip
  60         if (ret)
  61                 return ret;
  62
  63 +       if (misc2) {
  64 +               ret = regmap_update_bits(qpcs->regmap, PCS_MISC2,
  65 +                                        PCS_MISC2_MODE_MASK, misc2);
  66 +               if (ret)
  67 +                       return ret;
  68 +       }
  69 +
  70         /* PCS PLL reset */
  71         ret = regmap_clear_bits(qpcs->regmap, PCS_PLL_RESET, PCS_ANA_SW_RESET);
  72         if (ret)