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1 From 626cdca5b68acdc72d2533e2ed2306c06f296725 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Fri, 10 Jan 2025 16:41:13 +0800
4 Subject: [PATCH 1/3] net: mediatek: split ethernet switch code from mtk_eth.c
5
6 mtk_eth.c contains not only the ethernet GMAC/DMA driver, but also
7 some ethernet switch initialization code. As we may add more switch
8 support in the future, it's better to move them out of mtk_eth.c to
9 avoid increasing the code complexity.
10
11 Since not all switches are supported for a particular board, Kconfig
12 options are added to allow user to select which switch should be
13 built into u-boot. If multiple switches are selected, auto-detecting
14 can also be enabled.
15
16 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
17 ---
18 drivers/net/Kconfig | 21 +-
19 drivers/net/Makefile | 2 +-
20 drivers/net/mtk_eth/Kconfig | 35 +
21 drivers/net/mtk_eth/Makefile | 9 +
22 drivers/net/mtk_eth/mt7530.c | 281 ++++++++
23 drivers/net/mtk_eth/mt7531.c | 293 +++++++++
24 drivers/net/mtk_eth/mt753x.c | 262 ++++++++
25 drivers/net/mtk_eth/mt753x.h | 286 ++++++++
26 drivers/net/mtk_eth/mt7988.c | 160 +++++
27 drivers/net/{ => mtk_eth}/mtk_eth.c | 971 ++++------------------------
28 drivers/net/{ => mtk_eth}/mtk_eth.h | 301 ++-------
29 11 files changed, 1520 insertions(+), 1101 deletions(-)
30 create mode 100644 drivers/net/mtk_eth/Kconfig
31 create mode 100644 drivers/net/mtk_eth/Makefile
32 create mode 100644 drivers/net/mtk_eth/mt7530.c
33 create mode 100644 drivers/net/mtk_eth/mt7531.c
34 create mode 100644 drivers/net/mtk_eth/mt753x.c
35 create mode 100644 drivers/net/mtk_eth/mt753x.h
36 create mode 100644 drivers/net/mtk_eth/mt7988.c
37 rename drivers/net/{ => mtk_eth}/mtk_eth.c (62%)
38 rename drivers/net/{ => mtk_eth}/mtk_eth.h (59%)
39
40 --- a/drivers/net/Kconfig
41 +++ b/drivers/net/Kconfig
42 @@ -966,26 +966,7 @@ config TSEC_ENET
43 This driver implements support for the (Enhanced) Three-Speed
44 Ethernet Controller found on Freescale SoCs.
45
46 -config MEDIATEK_ETH
47 - bool "MediaTek Ethernet GMAC Driver"
48 - select PHYLIB
49 - select DM_GPIO
50 - select DM_RESET
51 - help
52 - This Driver support MediaTek Ethernet GMAC
53 - Say Y to enable support for the MediaTek Ethernet GMAC.
54 -
55 -if MEDIATEK_ETH
56 -
57 -config MTK_ETH_SGMII
58 - bool
59 - default y if ARCH_MEDIATEK && !TARGET_MT7623
60 -
61 -config MTK_ETH_XGMII
62 - bool
63 - default y if TARGET_MT7987 || TARGET_MT7988
64 -
65 -endif # MEDIATEK_ETH
66 +source "drivers/net/mtk_eth/Kconfig"
67
68 config HIFEMAC_ETH
69 bool "HiSilicon Fast Ethernet Controller"
70 --- a/drivers/net/Makefile
71 +++ b/drivers/net/Makefile
72 @@ -67,7 +67,7 @@ obj-$(CONFIG_MDIO_MUX_MESON_GXL) += mdio
73 obj-$(CONFIG_MDIO_MUX_MMIOREG) += mdio_mux_mmioreg.o
74 obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
75 obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
76 -obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
77 +obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth/
78 obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
79 obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o
80 obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o
81 --- /dev/null
82 +++ b/drivers/net/mtk_eth/Kconfig
83 @@ -0,0 +1,35 @@
84 +
85 +config MEDIATEK_ETH
86 + bool "MediaTek Ethernet GMAC Driver"
87 + select PHYLIB
88 + select DM_GPIO
89 + select DM_RESET
90 + help
91 + This Driver support MediaTek Ethernet GMAC
92 + Say Y to enable support for the MediaTek Ethernet GMAC.
93 +
94 +if MEDIATEK_ETH
95 +
96 +config MTK_ETH_SGMII
97 + bool
98 + default y if ARCH_MEDIATEK && !TARGET_MT7623
99 +
100 +config MTK_ETH_XGMII
101 + bool
102 + default y if TARGET_MT7988
103 +
104 +config MTK_ETH_SWITCH_MT7530
105 + bool "Support for MediaTek MT7530 ethernet switch"
106 + default y if TARGET_MT7623 || SOC_MT7621
107 +
108 +config MTK_ETH_SWITCH_MT7531
109 + bool "Support for MediaTek MT7531 ethernet switch"
110 + default y if TARGET_MT7622 || TARGET_MT7629 || TARGET_MT7981 || \
111 + TARGET_MT7986
112 +
113 +config MTK_ETH_SWITCH_MT7988
114 + bool "Support for MediaTek MT7988 built-in ethernet switch"
115 + depends on TARGET_MT7988
116 + default y
117 +
118 +endif # MEDIATEK_ETH
119 --- /dev/null
120 +++ b/drivers/net/mtk_eth/Makefile
121 @@ -0,0 +1,9 @@
122 +# SPDX-License-Identifier: GPL-2.0+
123 +#
124 +# Copyright (C) 2025 MediaTek Inc.
125 +# Author: Weijie Gao <weijie.gao@mediatek.com>
126 +
127 +obj-y += mtk_eth.o
128 +obj-$(CONFIG_MTK_ETH_SWITCH_MT7530) += mt753x.o mt7530.o
129 +obj-$(CONFIG_MTK_ETH_SWITCH_MT7531) += mt753x.o mt7531.o
130 +obj-$(CONFIG_MTK_ETH_SWITCH_MT7988) += mt753x.o mt7988.o
131 --- /dev/null
132 +++ b/drivers/net/mtk_eth/mt7530.c
133 @@ -0,0 +1,281 @@
134 +// SPDX-License-Identifier: GPL-2.0
135 +/*
136 + * Copyright (C) 2025 MediaTek Inc.
137 + *
138 + * Author: Weijie Gao <weijie.gao@mediatek.com>
139 + * Author: Mark Lee <mark-mc.lee@mediatek.com>
140 + */
141 +
142 +#include <miiphy.h>
143 +#include <linux/delay.h>
144 +#include <linux/mdio.h>
145 +#include <linux/mii.h>
146 +#include "mtk_eth.h"
147 +#include "mt753x.h"
148 +
149 +#define CHIP_REV 0x7ffc
150 +#define CHIP_NAME_S 16
151 +#define CHIP_NAME_M 0xffff0000
152 +#define CHIP_REV_S 0
153 +#define CHIP_REV_M 0x0f
154 +
155 +static void mt7530_core_reg_write(struct mt753x_switch_priv *priv, u32 reg,
156 + u32 val)
157 +{
158 + u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0);
159 +
160 + mtk_mmd_ind_write(priv->epriv.eth, phy_addr, 0x1f, reg, val);
161 +}
162 +
163 +static int mt7530_pad_clk_setup(struct mt753x_switch_priv *priv, int mode)
164 +{
165 + u32 ncpo1, ssc_delta;
166 +
167 + switch (mode) {
168 + case PHY_INTERFACE_MODE_RGMII:
169 + ncpo1 = 0x0c80;
170 + ssc_delta = 0x87;
171 + break;
172 +
173 + default:
174 + printf("error: xMII mode %d is not supported\n", mode);
175 + return -EINVAL;
176 + }
177 +
178 + /* Disable MT7530 core clock */
179 + mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0);
180 +
181 + /* Disable MT7530 PLL */
182 + mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1,
183 + (2 << RG_GSWPLL_POSDIV_200M_S) |
184 + (32 << RG_GSWPLL_FBKDIV_200M_S));
185 +
186 + /* For MT7530 core clock = 500Mhz */
187 + mt7530_core_reg_write(priv, CORE_GSWPLL_GRP2,
188 + (1 << RG_GSWPLL_POSDIV_500M_S) |
189 + (25 << RG_GSWPLL_FBKDIV_500M_S));
190 +
191 + /* Enable MT7530 PLL */
192 + mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1,
193 + (2 << RG_GSWPLL_POSDIV_200M_S) |
194 + (32 << RG_GSWPLL_FBKDIV_200M_S) |
195 + RG_GSWPLL_EN_PRE);
196 +
197 + udelay(20);
198 +
199 + mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
200 +
201 + /* Setup the MT7530 TRGMII Tx Clock */
202 + mt7530_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1);
203 + mt7530_core_reg_write(priv, CORE_PLL_GROUP6, 0);
204 + mt7530_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta);
205 + mt7530_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta);
206 + mt7530_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
207 + RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
208 +
209 + mt7530_core_reg_write(priv, CORE_PLL_GROUP2,
210 + RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
211 + (1 << RG_SYSPLL_POSDIV_S));
212 +
213 + mt7530_core_reg_write(priv, CORE_PLL_GROUP7,
214 + RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) |
215 + RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
216 +
217 + /* Enable MT7530 core clock */
218 + mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG,
219 + REG_GSWCK_EN | REG_TRGMIICK_EN);
220 +
221 + return 0;
222 +}
223 +
224 +static void mt7530_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable)
225 +{
226 + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv;
227 + u32 pmcr = FORCE_MODE;
228 +
229 + if (enable)
230 + pmcr = priv->pmcr;
231 +
232 + mt753x_reg_write(priv, PMCR_REG(6), pmcr);
233 +}
234 +
235 +static int mt7530_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
236 +{
237 + struct mt753x_switch_priv *priv = bus->priv;
238 +
239 + if (devad < 0)
240 + return mtk_mii_read(priv->epriv.eth, addr, reg);
241 +
242 + return mtk_mmd_ind_read(priv->epriv.eth, addr, devad, reg);
243 +}
244 +
245 +static int mt7530_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
246 + u16 val)
247 +{
248 + struct mt753x_switch_priv *priv = bus->priv;
249 +
250 + if (devad < 0)
251 + return mtk_mii_write(priv->epriv.eth, addr, reg, val);
252 +
253 + return mtk_mmd_ind_write(priv->epriv.eth, addr, devad, reg, val);
254 +}
255 +
256 +static int mt7530_mdio_register(struct mt753x_switch_priv *priv)
257 +{
258 + struct mii_dev *mdio_bus = mdio_alloc();
259 + int ret;
260 +
261 + if (!mdio_bus)
262 + return -ENOMEM;
263 +
264 + mdio_bus->read = mt7530_mdio_read;
265 + mdio_bus->write = mt7530_mdio_write;
266 + snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name);
267 +
268 + mdio_bus->priv = priv;
269 +
270 + ret = mdio_register(mdio_bus);
271 + if (ret) {
272 + mdio_free(mdio_bus);
273 + return ret;
274 + }
275 +
276 + priv->mdio_bus = mdio_bus;
277 +
278 + return 0;
279 +}
280 +
281 +static int mt7530_setup(struct mtk_eth_switch_priv *swpriv)
282 +{
283 + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv;
284 + u16 phy_addr, phy_val;
285 + u32 i, val, txdrv;
286 +
287 + priv->smi_addr = MT753X_DFL_SMI_ADDR;
288 + priv->reg_read = mt753x_mdio_reg_read;
289 + priv->reg_write = mt753x_mdio_reg_write;
290 +
291 + if (!MTK_HAS_CAPS(priv->epriv.soc->caps, MTK_TRGMII_MT7621_CLK)) {
292 + /* Select 250MHz clk for RGMII mode */
293 + mtk_ethsys_rmw(priv->epriv.eth, ETHSYS_CLKCFG0_REG,
294 + ETHSYS_TRGMII_CLK_SEL362_5, 0);
295 +
296 + txdrv = 8;
297 + } else {
298 + txdrv = 4;
299 + }
300 +
301 + /* Modify HWTRAP first to allow direct access to internal PHYs */
302 + mt753x_reg_read(priv, HWTRAP_REG, &val);
303 + val |= CHG_TRAP;
304 + val &= ~C_MDIO_BPS;
305 + mt753x_reg_write(priv, MHWTRAP_REG, val);
306 +
307 + /* Calculate the phy base address */
308 + val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3;
309 + priv->phy_base = (val | 0x7) + 1;
310 +
311 + /* Turn off PHYs */
312 + for (i = 0; i < MT753X_NUM_PHYS; i++) {
313 + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i);
314 + phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR);
315 + phy_val |= BMCR_PDOWN;
316 + mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val);
317 + }
318 +
319 + /* Force MAC link down before reset */
320 + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
321 + mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
322 +
323 + /* MT7530 reset */
324 + mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
325 + udelay(100);
326 +
327 + val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
328 + MAC_MODE | FORCE_MODE |
329 + MAC_TX_EN | MAC_RX_EN |
330 + BKOFF_EN | BACKPR_EN |
331 + (SPEED_1000M << FORCE_SPD_S) |
332 + FORCE_DPX | FORCE_LINK;
333 +
334 + /* MT7530 Port6: Forced 1000M/FD, FC disabled */
335 + priv->pmcr = val;
336 +
337 + /* MT7530 Port5: Forced link down */
338 + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
339 +
340 + /* Keep MAC link down before starting eth */
341 + mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
342 +
343 + /* MT7530 Port6: Set to RGMII */
344 + mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
345 +
346 + /* Hardware Trap: Enable Port6, Disable Port5 */
347 + mt753x_reg_read(priv, HWTRAP_REG, &val);
348 + val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS |
349 + (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) |
350 + (P5_INTF_MODE_RGMII << P5_INTF_MODE_S);
351 + val &= ~(C_MDIO_BPS | P6_INTF_DIS);
352 + mt753x_reg_write(priv, MHWTRAP_REG, val);
353 +
354 + /* Setup switch core pll */
355 + mt7530_pad_clk_setup(priv, priv->epriv.phy_interface);
356 +
357 + /* Lower Tx Driving for TRGMII path */
358 + for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
359 + mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
360 + (txdrv << TD_DM_DRVP_S) |
361 + (txdrv << TD_DM_DRVN_S));
362 +
363 + for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
364 + mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
365 +
366 + /* Enable port isolation to block inter-port communication */
367 + mt753x_port_isolation(priv);
368 +
369 + /* Turn on PHYs */
370 + for (i = 0; i < MT753X_NUM_PHYS; i++) {
371 + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i);
372 + phy_val = mtk_mii_read(priv->epriv.eth, phy_addr, MII_BMCR);
373 + phy_val &= ~BMCR_PDOWN;
374 + mtk_mii_write(priv->epriv.eth, phy_addr, MII_BMCR, phy_val);
375 + }
376 +
377 + return mt7530_mdio_register(priv);
378 +}
379 +
380 +static int mt7530_cleanup(struct mtk_eth_switch_priv *swpriv)
381 +{
382 + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv;
383 +
384 + mdio_unregister(priv->mdio_bus);
385 +
386 + return 0;
387 +}
388 +
389 +static int mt7530_detect(struct mtk_eth_priv *priv)
390 +{
391 + int ret;
392 + u32 rev;
393 +
394 + ret = __mt753x_mdio_reg_read(priv, MT753X_DFL_SMI_ADDR, CHIP_REV, &rev);
395 + if (ret)
396 + return ret;
397 +
398 + if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == 0x7530)
399 + return 0;
400 +
401 + return -ENODEV;
402 +}
403 +
404 +MTK_ETH_SWITCH(mt7530) = {
405 + .name = "mt7530",
406 + .desc = "MediaTek MT7530",
407 + .priv_size = sizeof(struct mt753x_switch_priv),
408 + .reset_wait_time = 1000,
409 +
410 + .detect = mt7530_detect,
411 + .setup = mt7530_setup,
412 + .cleanup = mt7530_cleanup,
413 + .mac_control = mt7530_mac_control,
414 +};
415 --- /dev/null
416 +++ b/drivers/net/mtk_eth/mt7531.c
417 @@ -0,0 +1,293 @@
418 +// SPDX-License-Identifier: GPL-2.0
419 +/*
420 + * Copyright (C) 2025 MediaTek Inc.
421 + *
422 + * Author: Weijie Gao <weijie.gao@mediatek.com>
423 + * Author: Mark Lee <mark-mc.lee@mediatek.com>
424 + */
425 +
426 +#include <miiphy.h>
427 +#include <linux/delay.h>
428 +#include <linux/mdio.h>
429 +#include <linux/mii.h>
430 +#include "mtk_eth.h"
431 +#include "mt753x.h"
432 +
433 +#define CHIP_REV 0x781C
434 +#define CHIP_NAME_S 16
435 +#define CHIP_NAME_M 0xffff0000
436 +#define CHIP_REV_S 0
437 +#define CHIP_REV_M 0x0f
438 +#define CHIP_REV_E1 0x0
439 +
440 +static int mt7531_core_reg_read(struct mt753x_switch_priv *priv, u32 reg)
441 +{
442 + u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0);
443 +
444 + return mt7531_mmd_read(priv, phy_addr, 0x1f, reg);
445 +}
446 +
447 +static void mt7531_core_reg_write(struct mt753x_switch_priv *priv, u32 reg,
448 + u32 val)
449 +{
450 + u8 phy_addr = MT753X_PHY_ADDR(priv->phy_base, 0);
451 +
452 + mt7531_mmd_write(priv, phy_addr, 0x1f, reg, val);
453 +}
454 +
455 +static void mt7531_core_pll_setup(struct mt753x_switch_priv *priv)
456 +{
457 + /* Step 1 : Disable MT7531 COREPLL */
458 + mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0);
459 +
460 + /* Step 2: switch to XTAL output */
461 + mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW);
462 +
463 + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0);
464 +
465 + /* Step 3: disable PLLGP and enable program PLLGP */
466 + mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP);
467 +
468 + /* Step 4: program COREPLL output frequency to 500MHz */
469 + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M,
470 + 2 << RG_COREPLL_POSDIV_S);
471 + udelay(25);
472 +
473 + /* Currently, support XTAL 25Mhz only */
474 + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M,
475 + 0x140000 << RG_COREPLL_SDM_PCW_S);
476 +
477 + /* Set feedback divide ratio update signal to high */
478 + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG,
479 + RG_COREPLL_SDM_PCW_CHG);
480 +
481 + /* Wait for at least 16 XTAL clocks */
482 + udelay(10);
483 +
484 + /* Step 5: set feedback divide ratio update signal to low */
485 + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0);
486 +
487 + /* add enable 325M clock for SGMII */
488 + mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
489 +
490 + /* add enable 250SSC clock for RGMII */
491 + mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
492 +
493 + /*Step 6: Enable MT7531 PLL */
494 + mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN);
495 +
496 + mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL);
497 +
498 + udelay(25);
499 +}
500 +
501 +static int mt7531_port_sgmii_init(struct mt753x_switch_priv *priv, u32 port)
502 +{
503 + if (port != 5 && port != 6) {
504 + printf("mt7531: port %d is not a SGMII port\n", port);
505 + return -EINVAL;
506 + }
507 +
508 + /* Set SGMII GEN2 speed(2.5G) */
509 + mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK,
510 + FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500));
511 +
512 + /* Disable SGMII AN */
513 + mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port),
514 + SGMII_AN_ENABLE, 0);
515 +
516 + /* SGMII force mode setting */
517 + mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE);
518 +
519 + /* Release PHYA power down state */
520 + mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
521 + SGMII_PHYA_PWD, 0);
522 +
523 + return 0;
524 +}
525 +
526 +static int mt7531_port_rgmii_init(struct mt753x_switch_priv *priv, u32 port)
527 +{
528 + u32 val;
529 +
530 + if (port != 5) {
531 + printf("error: RGMII mode is not available for port %d\n",
532 + port);
533 + return -EINVAL;
534 + }
535 +
536 + mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val);
537 + val |= GP_CLK_EN;
538 + val &= ~GP_MODE_M;
539 + val |= GP_MODE_RGMII << GP_MODE_S;
540 + val |= TXCLK_NO_REVERSE;
541 + val |= RXCLK_NO_DELAY;
542 + val &= ~CLK_SKEW_IN_M;
543 + val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S;
544 + val &= ~CLK_SKEW_OUT_M;
545 + val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S;
546 + mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val);
547 +
548 + return 0;
549 +}
550 +
551 +static void mt7531_phy_setting(struct mt753x_switch_priv *priv)
552 +{
553 + int i;
554 + u32 val;
555 +
556 + for (i = 0; i < MT753X_NUM_PHYS; i++) {
557 + /* Enable HW auto downshift */
558 + mt7531_mii_write(priv, i, 0x1f, 0x1);
559 + val = mt7531_mii_read(priv, i, PHY_EXT_REG_14);
560 + val |= PHY_EN_DOWN_SHFIT;
561 + mt7531_mii_write(priv, i, PHY_EXT_REG_14, val);
562 +
563 + /* PHY link down power saving enable */
564 + val = mt7531_mii_read(priv, i, PHY_EXT_REG_17);
565 + val |= PHY_LINKDOWN_POWER_SAVING_EN;
566 + mt7531_mii_write(priv, i, PHY_EXT_REG_17, val);
567 +
568 + val = mt7531_mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6);
569 + val &= ~PHY_POWER_SAVING_M;
570 + val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
571 + mt7531_mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val);
572 + }
573 +}
574 +
575 +static void mt7531_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable)
576 +{
577 + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv;
578 + u32 pmcr = FORCE_MODE_LNK;
579 +
580 + if (enable)
581 + pmcr = priv->pmcr;
582 +
583 + mt753x_reg_write(priv, PMCR_REG(5), pmcr);
584 + mt753x_reg_write(priv, PMCR_REG(6), pmcr);
585 +}
586 +
587 +static int mt7531_setup(struct mtk_eth_switch_priv *swpriv)
588 +{
589 + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv;
590 + u32 i, val, pmcr, port5_sgmii;
591 + u16 phy_addr, phy_val;
592 +
593 + priv->smi_addr = MT753X_DFL_SMI_ADDR;
594 + priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK;
595 + priv->reg_read = mt753x_mdio_reg_read;
596 + priv->reg_write = mt753x_mdio_reg_write;
597 +
598 + /* Turn off PHYs */
599 + for (i = 0; i < MT753X_NUM_PHYS; i++) {
600 + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i);
601 + phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR);
602 + phy_val |= BMCR_PDOWN;
603 + mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val);
604 + }
605 +
606 + /* Force MAC link down before reset */
607 + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
608 + mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
609 +
610 + /* Switch soft reset */
611 + mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
612 + udelay(100);
613 +
614 + /* Enable MDC input Schmitt Trigger */
615 + mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN,
616 + SMT_IOLB_5_SMI_MDC_EN);
617 +
618 + mt7531_core_pll_setup(priv);
619 +
620 + mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val);
621 + port5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
622 +
623 + /* port5 support either RGMII or SGMII, port6 only support SGMII. */
624 + switch (priv->epriv.phy_interface) {
625 + case PHY_INTERFACE_MODE_RGMII:
626 + if (!port5_sgmii)
627 + mt7531_port_rgmii_init(priv, 5);
628 + break;
629 +
630 + case PHY_INTERFACE_MODE_2500BASEX:
631 + mt7531_port_sgmii_init(priv, 6);
632 + if (port5_sgmii)
633 + mt7531_port_sgmii_init(priv, 5);
634 + break;
635 +
636 + default:
637 + break;
638 + }
639 +
640 + pmcr = MT7531_FORCE_MODE |
641 + (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
642 + MAC_MODE | MAC_TX_EN | MAC_RX_EN |
643 + BKOFF_EN | BACKPR_EN |
644 + FORCE_RX_FC | FORCE_TX_FC |
645 + (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
646 + FORCE_LINK;
647 +
648 + priv->pmcr = pmcr;
649 +
650 + /* Keep MAC link down before starting eth */
651 + mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
652 + mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
653 +
654 + /* Enable port isolation to block inter-port communication */
655 + mt753x_port_isolation(priv);
656 +
657 + /* Turn on PHYs */
658 + for (i = 0; i < MT753X_NUM_PHYS; i++) {
659 + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i);
660 + phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR);
661 + phy_val &= ~BMCR_PDOWN;
662 + mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val);
663 + }
664 +
665 + mt7531_phy_setting(priv);
666 +
667 + /* Enable Internal PHYs */
668 + val = mt7531_core_reg_read(priv, CORE_PLL_GROUP4);
669 + val |= MT7531_BYPASS_MODE;
670 + val &= ~MT7531_POWER_ON_OFF;
671 + mt7531_core_reg_write(priv, CORE_PLL_GROUP4, val);
672 +
673 + return mt7531_mdio_register(priv);
674 +}
675 +
676 +static int mt7531_cleanup(struct mtk_eth_switch_priv *swpriv)
677 +{
678 + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv;
679 +
680 + mdio_unregister(priv->mdio_bus);
681 +
682 + return 0;
683 +}
684 +
685 +static int mt7531_detect(struct mtk_eth_priv *priv)
686 +{
687 + int ret;
688 + u32 rev;
689 +
690 + ret = __mt753x_mdio_reg_read(priv, MT753X_DFL_SMI_ADDR, CHIP_REV, &rev);
691 + if (ret)
692 + return ret;
693 +
694 + if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == 0x7531)
695 + return 0;
696 +
697 + return -ENODEV;
698 +}
699 +
700 +MTK_ETH_SWITCH(mt7531) = {
701 + .name = "mt7531",
702 + .desc = "MediaTek MT7531",
703 + .priv_size = sizeof(struct mt753x_switch_priv),
704 + .reset_wait_time = 200,
705 +
706 + .detect = mt7531_detect,
707 + .setup = mt7531_setup,
708 + .cleanup = mt7531_cleanup,
709 + .mac_control = mt7531_mac_control,
710 +};
711 --- /dev/null
712 +++ b/drivers/net/mtk_eth/mt753x.c
713 @@ -0,0 +1,262 @@
714 +// SPDX-License-Identifier: GPL-2.0
715 +/*
716 + * Copyright (C) 2025 MediaTek Inc.
717 + *
718 + * Author: Weijie Gao <weijie.gao@mediatek.com>
719 + * Author: Mark Lee <mark-mc.lee@mediatek.com>
720 + */
721 +
722 +#include <errno.h>
723 +#include <time.h>
724 +#include "mtk_eth.h"
725 +#include "mt753x.h"
726 +
727 +/*
728 + * MT753x Internal Register Address Bits
729 + * -------------------------------------------------------------------
730 + * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 |
731 + * |----------------------------------------|---------------|--------|
732 + * | Page Address | Reg Address | Unused |
733 + * -------------------------------------------------------------------
734 + */
735 +
736 +int __mt753x_mdio_reg_read(struct mtk_eth_priv *priv, u32 smi_addr, u32 reg,
737 + u32 *data)
738 +{
739 + int ret, low_word, high_word;
740 +
741 + /* Write page address */
742 + ret = mtk_mii_write(priv, smi_addr, 0x1f, reg >> 6);
743 + if (ret)
744 + return ret;
745 +
746 + /* Read low word */
747 + low_word = mtk_mii_read(priv, smi_addr, (reg >> 2) & 0xf);
748 + if (low_word < 0)
749 + return low_word;
750 +
751 + /* Read high word */
752 + high_word = mtk_mii_read(priv, smi_addr, 0x10);
753 + if (high_word < 0)
754 + return high_word;
755 +
756 + if (data)
757 + *data = ((u32)high_word << 16) | (low_word & 0xffff);
758 +
759 + return 0;
760 +}
761 +
762 +int mt753x_mdio_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data)
763 +{
764 + return __mt753x_mdio_reg_read(priv->epriv.eth, priv->smi_addr, reg,
765 + data);
766 +}
767 +
768 +int mt753x_mdio_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data)
769 +{
770 + int ret;
771 +
772 + /* Write page address */
773 + ret = mtk_mii_write(priv->epriv.eth, priv->smi_addr, 0x1f, reg >> 6);
774 + if (ret)
775 + return ret;
776 +
777 + /* Write low word */
778 + ret = mtk_mii_write(priv->epriv.eth, priv->smi_addr, (reg >> 2) & 0xf,
779 + data & 0xffff);
780 + if (ret)
781 + return ret;
782 +
783 + /* Write high word */
784 + return mtk_mii_write(priv->epriv.eth, priv->smi_addr, 0x10, data >> 16);
785 +}
786 +
787 +int mt753x_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data)
788 +{
789 + return priv->reg_read(priv, reg, data);
790 +}
791 +
792 +int mt753x_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data)
793 +{
794 + return priv->reg_write(priv, reg, data);
795 +}
796 +
797 +void mt753x_reg_rmw(struct mt753x_switch_priv *priv, u32 reg, u32 clr, u32 set)
798 +{
799 + u32 val;
800 +
801 + priv->reg_read(priv, reg, &val);
802 + val &= ~clr;
803 + val |= set;
804 + priv->reg_write(priv, reg, val);
805 +}
806 +
807 +/* Indirect MDIO clause 22/45 access */
808 +static int mt7531_mii_rw(struct mt753x_switch_priv *priv, int phy, int reg,
809 + u16 data, u32 cmd, u32 st)
810 +{
811 + u32 val, timeout_ms;
812 + ulong timeout;
813 + int ret = 0;
814 +
815 + val = (st << MDIO_ST_S) |
816 + ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
817 + ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
818 + ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
819 +
820 + if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
821 + val |= data & MDIO_RW_DATA_M;
822 +
823 + mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST);
824 +
825 + timeout_ms = 100;
826 + timeout = get_timer(0);
827 + while (1) {
828 + mt753x_reg_read(priv, MT7531_PHY_IAC, &val);
829 +
830 + if ((val & PHY_ACS_ST) == 0)
831 + break;
832 +
833 + if (get_timer(timeout) > timeout_ms)
834 + return -ETIMEDOUT;
835 + }
836 +
837 + if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
838 + mt753x_reg_read(priv, MT7531_PHY_IAC, &val);
839 + ret = val & MDIO_RW_DATA_M;
840 + }
841 +
842 + return ret;
843 +}
844 +
845 +int mt7531_mii_read(struct mt753x_switch_priv *priv, u8 phy, u8 reg)
846 +{
847 + u8 phy_addr;
848 +
849 + if (phy >= MT753X_NUM_PHYS)
850 + return -EINVAL;
851 +
852 + phy_addr = MT753X_PHY_ADDR(priv->phy_base, phy);
853 +
854 + return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ,
855 + MDIO_ST_C22);
856 +}
857 +
858 +int mt7531_mii_write(struct mt753x_switch_priv *priv, u8 phy, u8 reg, u16 val)
859 +{
860 + u8 phy_addr;
861 +
862 + if (phy >= MT753X_NUM_PHYS)
863 + return -EINVAL;
864 +
865 + phy_addr = MT753X_PHY_ADDR(priv->phy_base, phy);
866 +
867 + return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE,
868 + MDIO_ST_C22);
869 +}
870 +
871 +int mt7531_mmd_read(struct mt753x_switch_priv *priv, u8 addr, u8 devad,
872 + u16 reg)
873 +{
874 + u8 phy_addr;
875 + int ret;
876 +
877 + if (addr >= MT753X_NUM_PHYS)
878 + return -EINVAL;
879 +
880 + phy_addr = MT753X_PHY_ADDR(priv->phy_base, addr);
881 +
882 + ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR,
883 + MDIO_ST_C45);
884 + if (ret)
885 + return ret;
886 +
887 + return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45,
888 + MDIO_ST_C45);
889 +}
890 +
891 +int mt7531_mmd_write(struct mt753x_switch_priv *priv, u8 addr, u8 devad,
892 + u16 reg, u16 val)
893 +{
894 + u8 phy_addr;
895 + int ret;
896 +
897 + if (addr >= MT753X_NUM_PHYS)
898 + return 0;
899 +
900 + phy_addr = MT753X_PHY_ADDR(priv->phy_base, addr);
901 +
902 + ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR,
903 + MDIO_ST_C45);
904 + if (ret)
905 + return ret;
906 +
907 + return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE,
908 + MDIO_ST_C45);
909 +}
910 +
911 +static int mt7531_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
912 +{
913 + struct mt753x_switch_priv *priv = bus->priv;
914 +
915 + if (devad < 0)
916 + return mt7531_mii_read(priv, addr, reg);
917 +
918 + return mt7531_mmd_read(priv, addr, devad, reg);
919 +}
920 +
921 +static int mt7531_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
922 + u16 val)
923 +{
924 + struct mt753x_switch_priv *priv = bus->priv;
925 +
926 + if (devad < 0)
927 + return mt7531_mii_write(priv, addr, reg, val);
928 +
929 + return mt7531_mmd_write(priv, addr, devad, reg, val);
930 +}
931 +
932 +int mt7531_mdio_register(struct mt753x_switch_priv *priv)
933 +{
934 + struct mii_dev *mdio_bus = mdio_alloc();
935 + int ret;
936 +
937 + if (!mdio_bus)
938 + return -ENOMEM;
939 +
940 + mdio_bus->read = mt7531_mdio_read;
941 + mdio_bus->write = mt7531_mdio_write;
942 + snprintf(mdio_bus->name, sizeof(mdio_bus->name), priv->epriv.sw->name);
943 +
944 + mdio_bus->priv = priv;
945 +
946 + ret = mdio_register(mdio_bus);
947 + if (ret) {
948 + mdio_free(mdio_bus);
949 + return ret;
950 + }
951 +
952 + priv->mdio_bus = mdio_bus;
953 +
954 + return 0;
955 +}
956 +
957 +void mt753x_port_isolation(struct mt753x_switch_priv *priv)
958 +{
959 + u32 i;
960 +
961 + for (i = 0; i < MT753X_NUM_PORTS; i++) {
962 + /* Set port matrix mode */
963 + if (i != 6)
964 + mt753x_reg_write(priv, PCR_REG(i),
965 + (0x40 << PORT_MATRIX_S));
966 + else
967 + mt753x_reg_write(priv, PCR_REG(i),
968 + (0x3f << PORT_MATRIX_S));
969 +
970 + /* Set port mode to user port */
971 + mt753x_reg_write(priv, PVC_REG(i),
972 + (0x8100 << STAG_VPID_S) |
973 + (VLAN_ATTR_USER << VLAN_ATTR_S));
974 + }
975 +}
976 --- /dev/null
977 +++ b/drivers/net/mtk_eth/mt753x.h
978 @@ -0,0 +1,286 @@
979 +/* SPDX-License-Identifier: GPL-2.0 */
980 +/*
981 + * Copyright (C) 2025 MediaTek Inc.
982 + *
983 + * Author: Weijie Gao <weijie.gao@mediatek.com>
984 + * Author: Mark Lee <mark-mc.lee@mediatek.com>
985 + */
986 +
987 +#ifndef _MTK_ETH_MT753X_H_
988 +#define _MTK_ETH_MT753X_H_
989 +
990 +#include <phy.h>
991 +#include <miiphy.h>
992 +#include <linux/bitops.h>
993 +#include <linux/bitfield.h>
994 +
995 +struct mtk_eth_priv;
996 +
997 +#define MT753X_NUM_PHYS 5
998 +#define MT753X_NUM_PORTS 7
999 +#define MT753X_DFL_SMI_ADDR 31
1000 +#define MT753X_SMI_ADDR_MASK 0x1f
1001 +
1002 +#define MT753X_PHY_ADDR(base, addr) \
1003 + (((base) + (addr)) & 0x1f)
1004 +
1005 +/* MT7530 Registers */
1006 +#define PCR_REG(p) (0x2004 + (p) * 0x100)
1007 +#define PORT_MATRIX_S 16
1008 +#define PORT_MATRIX_M 0xff0000
1009 +
1010 +#define PVC_REG(p) (0x2010 + (p) * 0x100)
1011 +#define STAG_VPID_S 16
1012 +#define STAG_VPID_M 0xffff0000
1013 +#define VLAN_ATTR_S 6
1014 +#define VLAN_ATTR_M 0xc0
1015 +
1016 +/* VLAN_ATTR: VLAN attributes */
1017 +#define VLAN_ATTR_USER 0
1018 +#define VLAN_ATTR_STACK 1
1019 +#define VLAN_ATTR_TRANSLATION 2
1020 +#define VLAN_ATTR_TRANSPARENT 3
1021 +
1022 +#define PMCR_REG(p) (0x3000 + (p) * 0x100)
1023 +/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR
1024 + * MT7531 specific fields are defined below
1025 + */
1026 +#define FORCE_MODE_EEE1G BIT(25)
1027 +#define FORCE_MODE_EEE100 BIT(26)
1028 +#define FORCE_MODE_TX_FC BIT(27)
1029 +#define FORCE_MODE_RX_FC BIT(28)
1030 +#define FORCE_MODE_DPX BIT(29)
1031 +#define FORCE_MODE_SPD BIT(30)
1032 +#define FORCE_MODE_LNK BIT(31)
1033 +#define MT7531_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
1034 + FORCE_MODE_DPX | FORCE_MODE_SPD | \
1035 + FORCE_MODE_LNK
1036 +#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
1037 + FORCE_MODE_DPX | FORCE_MODE_SPD | \
1038 + FORCE_MODE_LNK
1039 +
1040 +/* MT7531 SGMII Registers */
1041 +#define MT7531_SGMII_REG_BASE 0x5000
1042 +#define MT7531_SGMII_REG_PORT_BASE 0x1000
1043 +#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
1044 + (p) * MT7531_SGMII_REG_PORT_BASE + (r))
1045 +#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00)
1046 +#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20)
1047 +#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8)
1048 +#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128)
1049 +#define MT7531_PHYA_ANA_SYSPLL(p) MT7531_SGMII_REG(((p) - 5), 0x158)
1050 +/* XXX: all fields of MT7531 SGMII are defined under SGMSYS */
1051 +
1052 +/* MT753x System Control Register */
1053 +#define SYS_CTRL_REG 0x7000
1054 +#define SW_PHY_RST BIT(2)
1055 +#define SW_SYS_RST BIT(1)
1056 +#define SW_REG_RST BIT(0)
1057 +
1058 +/* MT7531 */
1059 +#define MT7531_PHY_IAC 0x701c
1060 +/* XXX: all fields are defined under GMAC_PIAC_REG */
1061 +
1062 +#define MT7531_CLKGEN_CTRL 0x7500
1063 +#define CLK_SKEW_OUT_S 8
1064 +#define CLK_SKEW_OUT_M 0x300
1065 +#define CLK_SKEW_IN_S 6
1066 +#define CLK_SKEW_IN_M 0xc0
1067 +#define RXCLK_NO_DELAY BIT(5)
1068 +#define TXCLK_NO_REVERSE BIT(4)
1069 +#define GP_MODE_S 1
1070 +#define GP_MODE_M 0x06
1071 +#define GP_CLK_EN BIT(0)
1072 +
1073 +/* Values of GP_MODE */
1074 +#define GP_MODE_RGMII 0
1075 +#define GP_MODE_MII 1
1076 +#define GP_MODE_REV_MII 2
1077 +
1078 +/* Values of CLK_SKEW_IN */
1079 +#define CLK_SKEW_IN_NO_CHANGE 0
1080 +#define CLK_SKEW_IN_DELAY_100PPS 1
1081 +#define CLK_SKEW_IN_DELAY_200PPS 2
1082 +#define CLK_SKEW_IN_REVERSE 3
1083 +
1084 +/* Values of CLK_SKEW_OUT */
1085 +#define CLK_SKEW_OUT_NO_CHANGE 0
1086 +#define CLK_SKEW_OUT_DELAY_100PPS 1
1087 +#define CLK_SKEW_OUT_DELAY_200PPS 2
1088 +#define CLK_SKEW_OUT_REVERSE 3
1089 +
1090 +#define HWTRAP_REG 0x7800
1091 +/* MT7530 Modified Hardware Trap Status Registers */
1092 +#define MHWTRAP_REG 0x7804
1093 +#define CHG_TRAP BIT(16)
1094 +#define LOOPDET_DIS BIT(14)
1095 +#define P5_INTF_SEL_S 13
1096 +#define P5_INTF_SEL_M 0x2000
1097 +#define SMI_ADDR_S 11
1098 +#define SMI_ADDR_M 0x1800
1099 +#define XTAL_FSEL_S 9
1100 +#define XTAL_FSEL_M 0x600
1101 +#define P6_INTF_DIS BIT(8)
1102 +#define P5_INTF_MODE_S 7
1103 +#define P5_INTF_MODE_M 0x80
1104 +#define P5_INTF_DIS BIT(6)
1105 +#define C_MDIO_BPS BIT(5)
1106 +#define CHIP_MODE_S 0
1107 +#define CHIP_MODE_M 0x0f
1108 +
1109 +/* P5_INTF_SEL: Interface type of Port5 */
1110 +#define P5_INTF_SEL_GPHY 0
1111 +#define P5_INTF_SEL_GMAC5 1
1112 +
1113 +/* P5_INTF_MODE: Interface mode of Port5 */
1114 +#define P5_INTF_MODE_GMII_MII 0
1115 +#define P5_INTF_MODE_RGMII 1
1116 +
1117 +#define MT7530_P6ECR 0x7830
1118 +#define P6_INTF_MODE_M 0x3
1119 +#define P6_INTF_MODE_S 0
1120 +
1121 +/* P6_INTF_MODE: Interface mode of Port6 */
1122 +#define P6_INTF_MODE_RGMII 0
1123 +#define P6_INTF_MODE_TRGMII 1
1124 +
1125 +#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8)
1126 +#define RD_TAP_S 0
1127 +#define RD_TAP_M 0x7f
1128 +
1129 +#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8)
1130 +/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */
1131 +
1132 +/* TOP Signals Status Register */
1133 +#define MT7531_TOP_SIG_SR 0x780c
1134 +#define PAD_MCM_SMI_EN BIT(0)
1135 +#define PAD_DUAL_SGMII_EN BIT(1)
1136 +
1137 +/* MT7531 PLLGP Registers */
1138 +#define MT7531_PLLGP_EN 0x7820
1139 +#define EN_COREPLL BIT(2)
1140 +#define SW_CLKSW BIT(1)
1141 +#define SW_PLLGP BIT(0)
1142 +
1143 +#define MT7531_PLLGP_CR0 0x78a8
1144 +#define RG_COREPLL_EN BIT(22)
1145 +#define RG_COREPLL_POSDIV_S 23
1146 +#define RG_COREPLL_POSDIV_M 0x3800000
1147 +#define RG_COREPLL_SDM_PCW_S 1
1148 +#define RG_COREPLL_SDM_PCW_M 0x3ffffe
1149 +#define RG_COREPLL_SDM_PCW_CHG BIT(0)
1150 +
1151 +/* MT7531 RGMII and SGMII PLL clock */
1152 +#define MT7531_ANA_PLLGP_CR2 0x78b0
1153 +#define MT7531_ANA_PLLGP_CR5 0x78bc
1154 +
1155 +/* MT7531 GPIO GROUP IOLB SMT0 Control */
1156 +#define MT7531_SMT0_IOLB 0x7f04
1157 +#define SMT_IOLB_5_SMI_MDC_EN BIT(5)
1158 +
1159 +/* MT7530 GPHY MDIO MMD Registers */
1160 +#define CORE_PLL_GROUP2 0x401
1161 +#define RG_SYSPLL_EN_NORMAL BIT(15)
1162 +#define RG_SYSPLL_VODEN BIT(14)
1163 +#define RG_SYSPLL_POSDIV_S 5
1164 +#define RG_SYSPLL_POSDIV_M 0x60
1165 +
1166 +#define CORE_PLL_GROUP4 0x403
1167 +#define MT7531_BYPASS_MODE BIT(4)
1168 +#define MT7531_POWER_ON_OFF BIT(5)
1169 +#define RG_SYSPLL_DDSFBK_EN BIT(12)
1170 +#define RG_SYSPLL_BIAS_EN BIT(11)
1171 +#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
1172 +
1173 +#define CORE_PLL_GROUP5 0x404
1174 +#define RG_LCDDS_PCW_NCPO1_S 0
1175 +#define RG_LCDDS_PCW_NCPO1_M 0xffff
1176 +
1177 +#define CORE_PLL_GROUP6 0x405
1178 +#define RG_LCDDS_PCW_NCPO0_S 0
1179 +#define RG_LCDDS_PCW_NCPO0_M 0xffff
1180 +
1181 +#define CORE_PLL_GROUP7 0x406
1182 +#define RG_LCDDS_PWDB BIT(15)
1183 +#define RG_LCDDS_ISO_EN BIT(13)
1184 +#define RG_LCCDS_C_S 4
1185 +#define RG_LCCDS_C_M 0x70
1186 +#define RG_LCDDS_PCW_NCPO_CHG BIT(3)
1187 +
1188 +#define CORE_PLL_GROUP10 0x409
1189 +#define RG_LCDDS_SSC_DELTA_S 0
1190 +#define RG_LCDDS_SSC_DELTA_M 0xfff
1191 +
1192 +#define CORE_PLL_GROUP11 0x40a
1193 +#define RG_LCDDS_SSC_DELTA1_S 0
1194 +#define RG_LCDDS_SSC_DELTA1_M 0xfff
1195 +
1196 +#define CORE_GSWPLL_GRP1 0x40d
1197 +#define RG_GSWPLL_POSDIV_200M_S 12
1198 +#define RG_GSWPLL_POSDIV_200M_M 0x3000
1199 +#define RG_GSWPLL_EN_PRE BIT(11)
1200 +#define RG_GSWPLL_FBKDIV_200M_S 0
1201 +#define RG_GSWPLL_FBKDIV_200M_M 0xff
1202 +
1203 +#define CORE_GSWPLL_GRP2 0x40e
1204 +#define RG_GSWPLL_POSDIV_500M_S 8
1205 +#define RG_GSWPLL_POSDIV_500M_M 0x300
1206 +#define RG_GSWPLL_FBKDIV_500M_S 0
1207 +#define RG_GSWPLL_FBKDIV_500M_M 0xff
1208 +
1209 +#define CORE_TRGMII_GSW_CLK_CG 0x410
1210 +#define REG_GSWCK_EN BIT(0)
1211 +#define REG_TRGMIICK_EN BIT(1)
1212 +
1213 +/* Extend PHY Control Register 3 */
1214 +#define PHY_EXT_REG_14 0x14
1215 +
1216 +/* Fields of PHY_EXT_REG_14 */
1217 +#define PHY_EN_DOWN_SHFIT BIT(4)
1218 +
1219 +/* Extend PHY Control Register 4 */
1220 +#define PHY_EXT_REG_17 0x17
1221 +
1222 +/* Fields of PHY_EXT_REG_17 */
1223 +#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4)
1224 +
1225 +/* PHY RXADC Control Register 7 */
1226 +#define PHY_DEV1E_REG_0C6 0x0c6
1227 +
1228 +/* Fields of PHY_DEV1E_REG_0C6 */
1229 +#define PHY_POWER_SAVING_S 8
1230 +#define PHY_POWER_SAVING_M 0x300
1231 +#define PHY_POWER_SAVING_TX 0x0
1232 +
1233 +struct mt753x_switch_priv {
1234 + struct mtk_eth_switch_priv epriv;
1235 + struct mii_dev *mdio_bus;
1236 + u32 smi_addr;
1237 + u32 phy_base;
1238 + u32 pmcr;
1239 +
1240 + int (*reg_read)(struct mt753x_switch_priv *priv, u32 reg, u32 *data);
1241 + int (*reg_write)(struct mt753x_switch_priv *priv, u32 reg, u32 data);
1242 +};
1243 +
1244 +int __mt753x_mdio_reg_read(struct mtk_eth_priv *priv, u32 smi_addr, u32 reg,
1245 + u32 *data);
1246 +int mt753x_mdio_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data);
1247 +int mt753x_mdio_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data);
1248 +
1249 +int mt753x_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data);
1250 +int mt753x_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data);
1251 +void mt753x_reg_rmw(struct mt753x_switch_priv *priv, u32 reg, u32 clr, u32 set);
1252 +
1253 +int mt7531_mii_read(struct mt753x_switch_priv *priv, u8 phy, u8 reg);
1254 +int mt7531_mii_write(struct mt753x_switch_priv *priv, u8 phy, u8 reg, u16 val);
1255 +int mt7531_mmd_read(struct mt753x_switch_priv *priv, u8 addr, u8 devad,
1256 + u16 reg);
1257 +int mt7531_mmd_write(struct mt753x_switch_priv *priv, u8 addr, u8 devad,
1258 + u16 reg, u16 val);
1259 +
1260 +int mt7531_mdio_register(struct mt753x_switch_priv *priv);
1261 +
1262 +void mt753x_port_isolation(struct mt753x_switch_priv *priv);
1263 +
1264 +#endif /* _MTK_ETH_MT753X_H_ */
1265 --- /dev/null
1266 +++ b/drivers/net/mtk_eth/mt7988.c
1267 @@ -0,0 +1,160 @@
1268 +// SPDX-License-Identifier: GPL-2.0
1269 +/*
1270 + * Copyright (C) 2025 MediaTek Inc.
1271 + *
1272 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1273 + * Author: Mark Lee <mark-mc.lee@mediatek.com>
1274 + */
1275 +
1276 +#include <miiphy.h>
1277 +#include <linux/delay.h>
1278 +#include <linux/mdio.h>
1279 +#include <linux/mii.h>
1280 +#include <linux/io.h>
1281 +#include "mtk_eth.h"
1282 +#include "mt753x.h"
1283 +
1284 +static int mt7988_reg_read(struct mt753x_switch_priv *priv, u32 reg, u32 *data)
1285 +{
1286 + *data = readl(priv->epriv.ethsys_base + GSW_BASE + reg);
1287 +
1288 + return 0;
1289 +}
1290 +
1291 +static int mt7988_reg_write(struct mt753x_switch_priv *priv, u32 reg, u32 data)
1292 +{
1293 + writel(data, priv->epriv.ethsys_base + GSW_BASE + reg);
1294 +
1295 + return 0;
1296 +}
1297 +
1298 +static void mt7988_phy_setting(struct mt753x_switch_priv *priv)
1299 +{
1300 + u16 val;
1301 + u32 i;
1302 +
1303 + for (i = 0; i < MT753X_NUM_PHYS; i++) {
1304 + /* Enable HW auto downshift */
1305 + mt7531_mii_write(priv, i, 0x1f, 0x1);
1306 + val = mt7531_mii_read(priv, i, PHY_EXT_REG_14);
1307 + val |= PHY_EN_DOWN_SHFIT;
1308 + mt7531_mii_write(priv, i, PHY_EXT_REG_14, val);
1309 +
1310 + /* PHY link down power saving enable */
1311 + val = mt7531_mii_read(priv, i, PHY_EXT_REG_17);
1312 + val |= PHY_LINKDOWN_POWER_SAVING_EN;
1313 + mt7531_mii_write(priv, i, PHY_EXT_REG_17, val);
1314 + }
1315 +}
1316 +
1317 +static void mt7988_mac_control(struct mtk_eth_switch_priv *swpriv, bool enable)
1318 +{
1319 + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv;
1320 + u32 pmcr = FORCE_MODE_LNK;
1321 +
1322 + if (enable)
1323 + pmcr = priv->pmcr;
1324 +
1325 + mt7988_reg_write(priv, PMCR_REG(6), pmcr);
1326 +}
1327 +
1328 +static int mt7988_setup(struct mtk_eth_switch_priv *swpriv)
1329 +{
1330 + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv;
1331 + u16 phy_addr, phy_val;
1332 + u32 pmcr;
1333 + int i;
1334 +
1335 + priv->smi_addr = MT753X_DFL_SMI_ADDR;
1336 + priv->phy_base = (priv->smi_addr + 1) & MT753X_SMI_ADDR_MASK;
1337 + priv->reg_read = mt7988_reg_read;
1338 + priv->reg_write = mt7988_reg_write;
1339 +
1340 + /* Turn off PHYs */
1341 + for (i = 0; i < MT753X_NUM_PHYS; i++) {
1342 + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i);
1343 + phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR);
1344 + phy_val |= BMCR_PDOWN;
1345 + mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val);
1346 + }
1347 +
1348 + switch (priv->epriv.phy_interface) {
1349 + case PHY_INTERFACE_MODE_USXGMII:
1350 + /* Use CPU bridge instead of actual USXGMII path */
1351 +
1352 + /* Disable GDM1 RX CRC stripping */
1353 + /* mtk_fe_rmw(priv, 0x500, BIT(16), 0); */
1354 +
1355 + /* Set GDM1 no drop */
1356 + mtk_fe_rmw(priv->epriv.eth, PSE_NO_DROP_CFG_REG, 0,
1357 + PSE_NO_DROP_GDM1);
1358 +
1359 + /* Enable GSW CPU bridge as USXGMII */
1360 + /* mtk_fe_rmw(priv, 0x504, BIT(31), BIT(31)); */
1361 +
1362 + /* Enable GDM1 to GSW CPU bridge */
1363 + mtk_gmac_rmw(priv->epriv.eth, GMAC_MAC_MISC_REG, 0, BIT(0));
1364 +
1365 + /* XGMAC force link up */
1366 + mtk_gmac_rmw(priv->epriv.eth, GMAC_XGMAC_STS_REG, 0,
1367 + P1_XGMAC_FORCE_LINK);
1368 +
1369 + /* Setup GSW CPU bridge IPG */
1370 + mtk_gmac_rmw(priv->epriv.eth, GMAC_GSW_CFG_REG,
1371 + GSWTX_IPG_M | GSWRX_IPG_M,
1372 + (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S));
1373 + break;
1374 + default:
1375 + printf("Error: MT7988 GSW does not support %s interface\n",
1376 + phy_string_for_interface(priv->epriv.phy_interface));
1377 + break;
1378 + }
1379 +
1380 + pmcr = MT7988_FORCE_MODE |
1381 + (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
1382 + MAC_MODE | MAC_TX_EN | MAC_RX_EN |
1383 + BKOFF_EN | BACKPR_EN |
1384 + FORCE_RX_FC | FORCE_TX_FC |
1385 + (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
1386 + FORCE_LINK;
1387 +
1388 + priv->pmcr = pmcr;
1389 +
1390 + /* Keep MAC link down before starting eth */
1391 + mt7988_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
1392 +
1393 + /* Enable port isolation to block inter-port communication */
1394 + mt753x_port_isolation(priv);
1395 +
1396 + /* Turn on PHYs */
1397 + for (i = 0; i < MT753X_NUM_PHYS; i++) {
1398 + phy_addr = MT753X_PHY_ADDR(priv->phy_base, i);
1399 + phy_val = mt7531_mii_read(priv, phy_addr, MII_BMCR);
1400 + phy_val &= ~BMCR_PDOWN;
1401 + mt7531_mii_write(priv, phy_addr, MII_BMCR, phy_val);
1402 + }
1403 +
1404 + mt7988_phy_setting(priv);
1405 +
1406 + return mt7531_mdio_register(priv);
1407 +}
1408 +
1409 +static int mt7531_cleanup(struct mtk_eth_switch_priv *swpriv)
1410 +{
1411 + struct mt753x_switch_priv *priv = (struct mt753x_switch_priv *)swpriv;
1412 +
1413 + mdio_unregister(priv->mdio_bus);
1414 +
1415 + return 0;
1416 +}
1417 +
1418 +MTK_ETH_SWITCH(mt7988) = {
1419 + .name = "mt7988",
1420 + .desc = "MediaTek MT7988 built-in switch",
1421 + .priv_size = sizeof(struct mt753x_switch_priv),
1422 + .reset_wait_time = 50,
1423 +
1424 + .setup = mt7988_setup,
1425 + .cleanup = mt7531_cleanup,
1426 + .mac_control = mt7988_mac_control,
1427 +};
1428 --- a/drivers/net/mtk_eth.c
1429 +++ /dev/null
1430 @@ -1,2280 +0,0 @@
1431 -// SPDX-License-Identifier: GPL-2.0
1432 -/*
1433 - * Copyright (C) 2018 MediaTek Inc.
1434 - *
1435 - * Author: Weijie Gao <weijie.gao@mediatek.com>
1436 - * Author: Mark Lee <mark-mc.lee@mediatek.com>
1437 - */
1438 -
1439 -#include <cpu_func.h>
1440 -#include <dm.h>
1441 -#include <log.h>
1442 -#include <malloc.h>
1443 -#include <miiphy.h>
1444 -#include <net.h>
1445 -#include <regmap.h>
1446 -#include <reset.h>
1447 -#include <syscon.h>
1448 -#include <wait_bit.h>
1449 -#include <asm/cache.h>
1450 -#include <asm/gpio.h>
1451 -#include <asm/io.h>
1452 -#include <dm/device_compat.h>
1453 -#include <linux/delay.h>
1454 -#include <linux/err.h>
1455 -#include <linux/ioport.h>
1456 -#include <linux/mdio.h>
1457 -#include <linux/mii.h>
1458 -#include <linux/printk.h>
1459 -
1460 -#include "mtk_eth.h"
1461 -
1462 -#define NUM_TX_DESC 32
1463 -#define NUM_RX_DESC 32
1464 -#define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN)
1465 -#define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN)
1466 -#define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE)
1467 -
1468 -#define MT753X_NUM_PHYS 5
1469 -#define MT753X_NUM_PORTS 7
1470 -#define MT753X_DFL_SMI_ADDR 31
1471 -#define MT753X_SMI_ADDR_MASK 0x1f
1472 -
1473 -#define MT753X_PHY_ADDR(base, addr) \
1474 - (((base) + (addr)) & 0x1f)
1475 -
1476 -#define GDMA_FWD_TO_CPU \
1477 - (0x20000000 | \
1478 - GDM_ICS_EN | \
1479 - GDM_TCS_EN | \
1480 - GDM_UCS_EN | \
1481 - STRP_CRC | \
1482 - (DP_PDMA << MYMAC_DP_S) | \
1483 - (DP_PDMA << BC_DP_S) | \
1484 - (DP_PDMA << MC_DP_S) | \
1485 - (DP_PDMA << UN_DP_S))
1486 -
1487 -#define GDMA_BRIDGE_TO_CPU \
1488 - (0xC0000000 | \
1489 - GDM_ICS_EN | \
1490 - GDM_TCS_EN | \
1491 - GDM_UCS_EN | \
1492 - (DP_PDMA << MYMAC_DP_S) | \
1493 - (DP_PDMA << BC_DP_S) | \
1494 - (DP_PDMA << MC_DP_S) | \
1495 - (DP_PDMA << UN_DP_S))
1496 -
1497 -#define GDMA_FWD_DISCARD \
1498 - (0x20000000 | \
1499 - GDM_ICS_EN | \
1500 - GDM_TCS_EN | \
1501 - GDM_UCS_EN | \
1502 - STRP_CRC | \
1503 - (DP_DISCARD << MYMAC_DP_S) | \
1504 - (DP_DISCARD << BC_DP_S) | \
1505 - (DP_DISCARD << MC_DP_S) | \
1506 - (DP_DISCARD << UN_DP_S))
1507 -
1508 -enum mtk_switch {
1509 - SW_NONE,
1510 - SW_MT7530,
1511 - SW_MT7531,
1512 - SW_MT7988,
1513 -};
1514 -
1515 -/* struct mtk_soc_data - This is the structure holding all differences
1516 - * among various plaforms
1517 - * @caps Flags shown the extra capability for the SoC
1518 - * @ana_rgc3: The offset for register ANA_RGC3 related to
1519 - * sgmiisys syscon
1520 - * @gdma_count: Number of GDMAs
1521 - * @pdma_base: Register base of PDMA block
1522 - * @txd_size: Tx DMA descriptor size.
1523 - * @rxd_size: Rx DMA descriptor size.
1524 - */
1525 -struct mtk_soc_data {
1526 - u32 caps;
1527 - u32 ana_rgc3;
1528 - u32 gdma_count;
1529 - u32 pdma_base;
1530 - u32 txd_size;
1531 - u32 rxd_size;
1532 -};
1533 -
1534 -struct mtk_eth_priv {
1535 - char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
1536 -
1537 - void *tx_ring_noc;
1538 - void *rx_ring_noc;
1539 -
1540 - int rx_dma_owner_idx0;
1541 - int tx_cpu_owner_idx0;
1542 -
1543 - void __iomem *fe_base;
1544 - void __iomem *gmac_base;
1545 - void __iomem *sgmii_base;
1546 - void __iomem *gsw_base;
1547 -
1548 - struct regmap *ethsys_regmap;
1549 -
1550 - struct regmap *infra_regmap;
1551 -
1552 - struct regmap *usxgmii_regmap;
1553 - struct regmap *xfi_pextp_regmap;
1554 - struct regmap *xfi_pll_regmap;
1555 - struct regmap *toprgu_regmap;
1556 -
1557 - struct mii_dev *mdio_bus;
1558 - int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
1559 - int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
1560 - int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg);
1561 - int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
1562 - u16 val);
1563 -
1564 - const struct mtk_soc_data *soc;
1565 - int gmac_id;
1566 - int force_mode;
1567 - int speed;
1568 - int duplex;
1569 - int mdc;
1570 - bool pn_swap;
1571 -
1572 - struct phy_device *phydev;
1573 - int phy_interface;
1574 - int phy_addr;
1575 -
1576 - enum mtk_switch sw;
1577 - int (*switch_init)(struct mtk_eth_priv *priv);
1578 - void (*switch_mac_control)(struct mtk_eth_priv *priv, bool enable);
1579 - u32 mt753x_smi_addr;
1580 - u32 mt753x_phy_base;
1581 - u32 mt753x_pmcr;
1582 - u32 mt753x_reset_wait_time;
1583 -
1584 - struct gpio_desc rst_gpio;
1585 - int mcm;
1586 -
1587 - struct reset_ctl rst_fe;
1588 - struct reset_ctl rst_mcm;
1589 -};
1590 -
1591 -static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
1592 -{
1593 - writel(val, priv->fe_base + priv->soc->pdma_base + reg);
1594 -}
1595 -
1596 -static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
1597 - u32 set)
1598 -{
1599 - clrsetbits_le32(priv->fe_base + priv->soc->pdma_base + reg, clr, set);
1600 -}
1601 -
1602 -static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg,
1603 - u32 val)
1604 -{
1605 - u32 gdma_base;
1606 -
1607 - if (no == 2)
1608 - gdma_base = GDMA3_BASE;
1609 - else if (no == 1)
1610 - gdma_base = GDMA2_BASE;
1611 - else
1612 - gdma_base = GDMA1_BASE;
1613 -
1614 - writel(val, priv->fe_base + gdma_base + reg);
1615 -}
1616 -
1617 -static void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
1618 -{
1619 - clrsetbits_le32(priv->fe_base + reg, clr, set);
1620 -}
1621 -
1622 -static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
1623 -{
1624 - return readl(priv->gmac_base + reg);
1625 -}
1626 -
1627 -static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
1628 -{
1629 - writel(val, priv->gmac_base + reg);
1630 -}
1631 -
1632 -static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
1633 -{
1634 - clrsetbits_le32(priv->gmac_base + reg, clr, set);
1635 -}
1636 -
1637 -static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
1638 - u32 set)
1639 -{
1640 - uint val;
1641 -
1642 - regmap_read(priv->ethsys_regmap, reg, &val);
1643 - val &= ~clr;
1644 - val |= set;
1645 - regmap_write(priv->ethsys_regmap, reg, val);
1646 -}
1647 -
1648 -static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
1649 - u32 set)
1650 -{
1651 - uint val;
1652 -
1653 - regmap_read(priv->infra_regmap, reg, &val);
1654 - val &= ~clr;
1655 - val |= set;
1656 - regmap_write(priv->infra_regmap, reg, val);
1657 -}
1658 -
1659 -static u32 mtk_gsw_read(struct mtk_eth_priv *priv, u32 reg)
1660 -{
1661 - return readl(priv->gsw_base + reg);
1662 -}
1663 -
1664 -static void mtk_gsw_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
1665 -{
1666 - writel(val, priv->gsw_base + reg);
1667 -}
1668 -
1669 -/* Direct MDIO clause 22/45 access via SoC */
1670 -static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
1671 - u32 cmd, u32 st)
1672 -{
1673 - int ret;
1674 - u32 val;
1675 -
1676 - val = (st << MDIO_ST_S) |
1677 - ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
1678 - (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
1679 - (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
1680 -
1681 - if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
1682 - val |= data & MDIO_RW_DATA_M;
1683 -
1684 - mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
1685 -
1686 - ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG,
1687 - PHY_ACS_ST, 0, 5000, 0);
1688 - if (ret) {
1689 - pr_warn("MDIO access timeout\n");
1690 - return ret;
1691 - }
1692 -
1693 - if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
1694 - val = mtk_gmac_read(priv, GMAC_PIAC_REG);
1695 - return val & MDIO_RW_DATA_M;
1696 - }
1697 -
1698 - return 0;
1699 -}
1700 -
1701 -/* Direct MDIO clause 22 read via SoC */
1702 -static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
1703 -{
1704 - return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22);
1705 -}
1706 -
1707 -/* Direct MDIO clause 22 write via SoC */
1708 -static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data)
1709 -{
1710 - return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22);
1711 -}
1712 -
1713 -/* Direct MDIO clause 45 read via SoC */
1714 -static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
1715 -{
1716 - int ret;
1717 -
1718 - ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
1719 - if (ret)
1720 - return ret;
1721 -
1722 - return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45,
1723 - MDIO_ST_C45);
1724 -}
1725 -
1726 -/* Direct MDIO clause 45 write via SoC */
1727 -static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
1728 - u16 reg, u16 val)
1729 -{
1730 - int ret;
1731 -
1732 - ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
1733 - if (ret)
1734 - return ret;
1735 -
1736 - return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE,
1737 - MDIO_ST_C45);
1738 -}
1739 -
1740 -/* Indirect MDIO clause 45 read via MII registers */
1741 -static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
1742 - u16 reg)
1743 -{
1744 - int ret;
1745 -
1746 - ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
1747 - (MMD_ADDR << MMD_CMD_S) |
1748 - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
1749 - if (ret)
1750 - return ret;
1751 -
1752 - ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
1753 - if (ret)
1754 - return ret;
1755 -
1756 - ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
1757 - (MMD_DATA << MMD_CMD_S) |
1758 - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
1759 - if (ret)
1760 - return ret;
1761 -
1762 - return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG);
1763 -}
1764 -
1765 -/* Indirect MDIO clause 45 write via MII registers */
1766 -static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
1767 - u16 reg, u16 val)
1768 -{
1769 - int ret;
1770 -
1771 - ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
1772 - (MMD_ADDR << MMD_CMD_S) |
1773 - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
1774 - if (ret)
1775 - return ret;
1776 -
1777 - ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
1778 - if (ret)
1779 - return ret;
1780 -
1781 - ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
1782 - (MMD_DATA << MMD_CMD_S) |
1783 - ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
1784 - if (ret)
1785 - return ret;
1786 -
1787 - return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val);
1788 -}
1789 -
1790 -/*
1791 - * MT7530 Internal Register Address Bits
1792 - * -------------------------------------------------------------------
1793 - * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 |
1794 - * |----------------------------------------|---------------|--------|
1795 - * | Page Address | Reg Address | Unused |
1796 - * -------------------------------------------------------------------
1797 - */
1798 -
1799 -static int mt753x_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data)
1800 -{
1801 - int ret, low_word, high_word;
1802 -
1803 - if (priv->sw == SW_MT7988) {
1804 - *data = mtk_gsw_read(priv, reg);
1805 - return 0;
1806 - }
1807 -
1808 - /* Write page address */
1809 - ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
1810 - if (ret)
1811 - return ret;
1812 -
1813 - /* Read low word */
1814 - low_word = mtk_mii_read(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf);
1815 - if (low_word < 0)
1816 - return low_word;
1817 -
1818 - /* Read high word */
1819 - high_word = mtk_mii_read(priv, priv->mt753x_smi_addr, 0x10);
1820 - if (high_word < 0)
1821 - return high_word;
1822 -
1823 - if (data)
1824 - *data = ((u32)high_word << 16) | (low_word & 0xffff);
1825 -
1826 - return 0;
1827 -}
1828 -
1829 -static int mt753x_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data)
1830 -{
1831 - int ret;
1832 -
1833 - if (priv->sw == SW_MT7988) {
1834 - mtk_gsw_write(priv, reg, data);
1835 - return 0;
1836 - }
1837 -
1838 - /* Write page address */
1839 - ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6);
1840 - if (ret)
1841 - return ret;
1842 -
1843 - /* Write low word */
1844 - ret = mtk_mii_write(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf,
1845 - data & 0xffff);
1846 - if (ret)
1847 - return ret;
1848 -
1849 - /* Write high word */
1850 - return mtk_mii_write(priv, priv->mt753x_smi_addr, 0x10, data >> 16);
1851 -}
1852 -
1853 -static void mt753x_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
1854 - u32 set)
1855 -{
1856 - u32 val;
1857 -
1858 - mt753x_reg_read(priv, reg, &val);
1859 - val &= ~clr;
1860 - val |= set;
1861 - mt753x_reg_write(priv, reg, val);
1862 -}
1863 -
1864 -/* Indirect MDIO clause 22/45 access */
1865 -static int mt7531_mii_rw(struct mtk_eth_priv *priv, int phy, int reg, u16 data,
1866 - u32 cmd, u32 st)
1867 -{
1868 - ulong timeout;
1869 - u32 val, timeout_ms;
1870 - int ret = 0;
1871 -
1872 - val = (st << MDIO_ST_S) |
1873 - ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
1874 - ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
1875 - ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
1876 -
1877 - if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
1878 - val |= data & MDIO_RW_DATA_M;
1879 -
1880 - mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST);
1881 -
1882 - timeout_ms = 100;
1883 - timeout = get_timer(0);
1884 - while (1) {
1885 - mt753x_reg_read(priv, MT7531_PHY_IAC, &val);
1886 -
1887 - if ((val & PHY_ACS_ST) == 0)
1888 - break;
1889 -
1890 - if (get_timer(timeout) > timeout_ms)
1891 - return -ETIMEDOUT;
1892 - }
1893 -
1894 - if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
1895 - mt753x_reg_read(priv, MT7531_PHY_IAC, &val);
1896 - ret = val & MDIO_RW_DATA_M;
1897 - }
1898 -
1899 - return ret;
1900 -}
1901 -
1902 -static int mt7531_mii_ind_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
1903 -{
1904 - u8 phy_addr;
1905 -
1906 - if (phy >= MT753X_NUM_PHYS)
1907 - return -EINVAL;
1908 -
1909 - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy);
1910 -
1911 - return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ,
1912 - MDIO_ST_C22);
1913 -}
1914 -
1915 -static int mt7531_mii_ind_write(struct mtk_eth_priv *priv, u8 phy, u8 reg,
1916 - u16 val)
1917 -{
1918 - u8 phy_addr;
1919 -
1920 - if (phy >= MT753X_NUM_PHYS)
1921 - return -EINVAL;
1922 -
1923 - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy);
1924 -
1925 - return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE,
1926 - MDIO_ST_C22);
1927 -}
1928 -
1929 -static int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
1930 - u16 reg)
1931 -{
1932 - u8 phy_addr;
1933 - int ret;
1934 -
1935 - if (addr >= MT753X_NUM_PHYS)
1936 - return -EINVAL;
1937 -
1938 - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr);
1939 -
1940 - ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR,
1941 - MDIO_ST_C45);
1942 - if (ret)
1943 - return ret;
1944 -
1945 - return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45,
1946 - MDIO_ST_C45);
1947 -}
1948 -
1949 -static int mt7531_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
1950 - u16 reg, u16 val)
1951 -{
1952 - u8 phy_addr;
1953 - int ret;
1954 -
1955 - if (addr >= MT753X_NUM_PHYS)
1956 - return 0;
1957 -
1958 - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr);
1959 -
1960 - ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR,
1961 - MDIO_ST_C45);
1962 - if (ret)
1963 - return ret;
1964 -
1965 - return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE,
1966 - MDIO_ST_C45);
1967 -}
1968 -
1969 -static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
1970 -{
1971 - struct mtk_eth_priv *priv = bus->priv;
1972 -
1973 - if (devad < 0)
1974 - return priv->mii_read(priv, addr, reg);
1975 - else
1976 - return priv->mmd_read(priv, addr, devad, reg);
1977 -}
1978 -
1979 -static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
1980 - u16 val)
1981 -{
1982 - struct mtk_eth_priv *priv = bus->priv;
1983 -
1984 - if (devad < 0)
1985 - return priv->mii_write(priv, addr, reg, val);
1986 - else
1987 - return priv->mmd_write(priv, addr, devad, reg, val);
1988 -}
1989 -
1990 -static int mtk_mdio_register(struct udevice *dev)
1991 -{
1992 - struct mtk_eth_priv *priv = dev_get_priv(dev);
1993 - struct mii_dev *mdio_bus = mdio_alloc();
1994 - int ret;
1995 -
1996 - if (!mdio_bus)
1997 - return -ENOMEM;
1998 -
1999 - /* Assign MDIO access APIs according to the switch/phy */
2000 - switch (priv->sw) {
2001 - case SW_MT7530:
2002 - priv->mii_read = mtk_mii_read;
2003 - priv->mii_write = mtk_mii_write;
2004 - priv->mmd_read = mtk_mmd_ind_read;
2005 - priv->mmd_write = mtk_mmd_ind_write;
2006 - break;
2007 - case SW_MT7531:
2008 - case SW_MT7988:
2009 - priv->mii_read = mt7531_mii_ind_read;
2010 - priv->mii_write = mt7531_mii_ind_write;
2011 - priv->mmd_read = mt7531_mmd_ind_read;
2012 - priv->mmd_write = mt7531_mmd_ind_write;
2013 - break;
2014 - default:
2015 - priv->mii_read = mtk_mii_read;
2016 - priv->mii_write = mtk_mii_write;
2017 - priv->mmd_read = mtk_mmd_read;
2018 - priv->mmd_write = mtk_mmd_write;
2019 - }
2020 -
2021 - mdio_bus->read = mtk_mdio_read;
2022 - mdio_bus->write = mtk_mdio_write;
2023 - snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name);
2024 -
2025 - mdio_bus->priv = (void *)priv;
2026 -
2027 - ret = mdio_register(mdio_bus);
2028 -
2029 - if (ret)
2030 - return ret;
2031 -
2032 - priv->mdio_bus = mdio_bus;
2033 -
2034 - return 0;
2035 -}
2036 -
2037 -static int mt753x_core_reg_read(struct mtk_eth_priv *priv, u32 reg)
2038 -{
2039 - u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0);
2040 -
2041 - return priv->mmd_read(priv, phy_addr, 0x1f, reg);
2042 -}
2043 -
2044 -static void mt753x_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
2045 -{
2046 - u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0);
2047 -
2048 - priv->mmd_write(priv, phy_addr, 0x1f, reg, val);
2049 -}
2050 -
2051 -static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode)
2052 -{
2053 - u32 ncpo1, ssc_delta;
2054 -
2055 - switch (mode) {
2056 - case PHY_INTERFACE_MODE_RGMII:
2057 - ncpo1 = 0x0c80;
2058 - ssc_delta = 0x87;
2059 - break;
2060 - default:
2061 - printf("error: xMII mode %d not supported\n", mode);
2062 - return -EINVAL;
2063 - }
2064 -
2065 - /* Disable MT7530 core clock */
2066 - mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0);
2067 -
2068 - /* Disable MT7530 PLL */
2069 - mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1,
2070 - (2 << RG_GSWPLL_POSDIV_200M_S) |
2071 - (32 << RG_GSWPLL_FBKDIV_200M_S));
2072 -
2073 - /* For MT7530 core clock = 500Mhz */
2074 - mt753x_core_reg_write(priv, CORE_GSWPLL_GRP2,
2075 - (1 << RG_GSWPLL_POSDIV_500M_S) |
2076 - (25 << RG_GSWPLL_FBKDIV_500M_S));
2077 -
2078 - /* Enable MT7530 PLL */
2079 - mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1,
2080 - (2 << RG_GSWPLL_POSDIV_200M_S) |
2081 - (32 << RG_GSWPLL_FBKDIV_200M_S) |
2082 - RG_GSWPLL_EN_PRE);
2083 -
2084 - udelay(20);
2085 -
2086 - mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
2087 -
2088 - /* Setup the MT7530 TRGMII Tx Clock */
2089 - mt753x_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1);
2090 - mt753x_core_reg_write(priv, CORE_PLL_GROUP6, 0);
2091 - mt753x_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta);
2092 - mt753x_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta);
2093 - mt753x_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
2094 - RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
2095 -
2096 - mt753x_core_reg_write(priv, CORE_PLL_GROUP2,
2097 - RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
2098 - (1 << RG_SYSPLL_POSDIV_S));
2099 -
2100 - mt753x_core_reg_write(priv, CORE_PLL_GROUP7,
2101 - RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) |
2102 - RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
2103 -
2104 - /* Enable MT7530 core clock */
2105 - mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG,
2106 - REG_GSWCK_EN | REG_TRGMIICK_EN);
2107 -
2108 - return 0;
2109 -}
2110 -
2111 -static void mt7530_mac_control(struct mtk_eth_priv *priv, bool enable)
2112 -{
2113 - u32 pmcr = FORCE_MODE;
2114 -
2115 - if (enable)
2116 - pmcr = priv->mt753x_pmcr;
2117 -
2118 - mt753x_reg_write(priv, PMCR_REG(6), pmcr);
2119 -}
2120 -
2121 -static int mt7530_setup(struct mtk_eth_priv *priv)
2122 -{
2123 - u16 phy_addr, phy_val;
2124 - u32 val, txdrv;
2125 - int i;
2126 -
2127 - if (!MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) {
2128 - /* Select 250MHz clk for RGMII mode */
2129 - mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
2130 - ETHSYS_TRGMII_CLK_SEL362_5, 0);
2131 -
2132 - txdrv = 8;
2133 - } else {
2134 - txdrv = 4;
2135 - }
2136 -
2137 - /* Modify HWTRAP first to allow direct access to internal PHYs */
2138 - mt753x_reg_read(priv, HWTRAP_REG, &val);
2139 - val |= CHG_TRAP;
2140 - val &= ~C_MDIO_BPS;
2141 - mt753x_reg_write(priv, MHWTRAP_REG, val);
2142 -
2143 - /* Calculate the phy base address */
2144 - val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3;
2145 - priv->mt753x_phy_base = (val | 0x7) + 1;
2146 -
2147 - /* Turn off PHYs */
2148 - for (i = 0; i < MT753X_NUM_PHYS; i++) {
2149 - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
2150 - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
2151 - phy_val |= BMCR_PDOWN;
2152 - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
2153 - }
2154 -
2155 - /* Force MAC link down before reset */
2156 - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
2157 - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
2158 -
2159 - /* MT7530 reset */
2160 - mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
2161 - udelay(100);
2162 -
2163 - val = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
2164 - MAC_MODE | FORCE_MODE |
2165 - MAC_TX_EN | MAC_RX_EN |
2166 - BKOFF_EN | BACKPR_EN |
2167 - (SPEED_1000M << FORCE_SPD_S) |
2168 - FORCE_DPX | FORCE_LINK;
2169 -
2170 - /* MT7530 Port6: Forced 1000M/FD, FC disabled */
2171 - priv->mt753x_pmcr = val;
2172 -
2173 - /* MT7530 Port5: Forced link down */
2174 - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE);
2175 -
2176 - /* Keep MAC link down before starting eth */
2177 - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE);
2178 -
2179 - /* MT7530 Port6: Set to RGMII */
2180 - mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
2181 -
2182 - /* Hardware Trap: Enable Port6, Disable Port5 */
2183 - mt753x_reg_read(priv, HWTRAP_REG, &val);
2184 - val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS |
2185 - (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) |
2186 - (P5_INTF_MODE_RGMII << P5_INTF_MODE_S);
2187 - val &= ~(C_MDIO_BPS | P6_INTF_DIS);
2188 - mt753x_reg_write(priv, MHWTRAP_REG, val);
2189 -
2190 - /* Setup switch core pll */
2191 - mt7530_pad_clk_setup(priv, priv->phy_interface);
2192 -
2193 - /* Lower Tx Driving for TRGMII path */
2194 - for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
2195 - mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
2196 - (txdrv << TD_DM_DRVP_S) |
2197 - (txdrv << TD_DM_DRVN_S));
2198 -
2199 - for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
2200 - mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
2201 -
2202 - /* Turn on PHYs */
2203 - for (i = 0; i < MT753X_NUM_PHYS; i++) {
2204 - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
2205 - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
2206 - phy_val &= ~BMCR_PDOWN;
2207 - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
2208 - }
2209 -
2210 - return 0;
2211 -}
2212 -
2213 -static void mt7531_core_pll_setup(struct mtk_eth_priv *priv, int mcm)
2214 -{
2215 - /* Step 1 : Disable MT7531 COREPLL */
2216 - mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0);
2217 -
2218 - /* Step 2: switch to XTAL output */
2219 - mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW);
2220 -
2221 - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0);
2222 -
2223 - /* Step 3: disable PLLGP and enable program PLLGP */
2224 - mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP);
2225 -
2226 - /* Step 4: program COREPLL output frequency to 500MHz */
2227 - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M,
2228 - 2 << RG_COREPLL_POSDIV_S);
2229 - udelay(25);
2230 -
2231 - /* Currently, support XTAL 25Mhz only */
2232 - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M,
2233 - 0x140000 << RG_COREPLL_SDM_PCW_S);
2234 -
2235 - /* Set feedback divide ratio update signal to high */
2236 - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG,
2237 - RG_COREPLL_SDM_PCW_CHG);
2238 -
2239 - /* Wait for at least 16 XTAL clocks */
2240 - udelay(10);
2241 -
2242 - /* Step 5: set feedback divide ratio update signal to low */
2243 - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0);
2244 -
2245 - /* add enable 325M clock for SGMII */
2246 - mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
2247 -
2248 - /* add enable 250SSC clock for RGMII */
2249 - mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
2250 -
2251 - /*Step 6: Enable MT7531 PLL */
2252 - mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN);
2253 -
2254 - mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL);
2255 -
2256 - udelay(25);
2257 -}
2258 -
2259 -static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv,
2260 - u32 port)
2261 -{
2262 - if (port != 5 && port != 6) {
2263 - printf("mt7531: port %d is not a SGMII port\n", port);
2264 - return -EINVAL;
2265 - }
2266 -
2267 - /* Set SGMII GEN2 speed(2.5G) */
2268 - mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK,
2269 - FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500));
2270 -
2271 - /* Disable SGMII AN */
2272 - mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port),
2273 - SGMII_AN_ENABLE, 0);
2274 -
2275 - /* SGMII force mode setting */
2276 - mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE);
2277 -
2278 - /* Release PHYA power down state */
2279 - mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2280 - SGMII_PHYA_PWD, 0);
2281 -
2282 - return 0;
2283 -}
2284 -
2285 -static int mt7531_port_rgmii_init(struct mtk_eth_priv *priv, u32 port)
2286 -{
2287 - u32 val;
2288 -
2289 - if (port != 5) {
2290 - printf("error: RGMII mode is not available for port %d\n",
2291 - port);
2292 - return -EINVAL;
2293 - }
2294 -
2295 - mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val);
2296 - val |= GP_CLK_EN;
2297 - val &= ~GP_MODE_M;
2298 - val |= GP_MODE_RGMII << GP_MODE_S;
2299 - val |= TXCLK_NO_REVERSE;
2300 - val |= RXCLK_NO_DELAY;
2301 - val &= ~CLK_SKEW_IN_M;
2302 - val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S;
2303 - val &= ~CLK_SKEW_OUT_M;
2304 - val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S;
2305 - mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val);
2306 -
2307 - return 0;
2308 -}
2309 -
2310 -static void mt7531_phy_setting(struct mtk_eth_priv *priv)
2311 -{
2312 - int i;
2313 - u32 val;
2314 -
2315 - for (i = 0; i < MT753X_NUM_PHYS; i++) {
2316 - /* Enable HW auto downshift */
2317 - priv->mii_write(priv, i, 0x1f, 0x1);
2318 - val = priv->mii_read(priv, i, PHY_EXT_REG_14);
2319 - val |= PHY_EN_DOWN_SHFIT;
2320 - priv->mii_write(priv, i, PHY_EXT_REG_14, val);
2321 -
2322 - /* PHY link down power saving enable */
2323 - val = priv->mii_read(priv, i, PHY_EXT_REG_17);
2324 - val |= PHY_LINKDOWN_POWER_SAVING_EN;
2325 - priv->mii_write(priv, i, PHY_EXT_REG_17, val);
2326 -
2327 - val = priv->mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6);
2328 - val &= ~PHY_POWER_SAVING_M;
2329 - val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;
2330 - priv->mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val);
2331 - }
2332 -}
2333 -
2334 -static void mt7531_mac_control(struct mtk_eth_priv *priv, bool enable)
2335 -{
2336 - u32 pmcr = FORCE_MODE_LNK;
2337 -
2338 - if (enable)
2339 - pmcr = priv->mt753x_pmcr;
2340 -
2341 - mt753x_reg_write(priv, PMCR_REG(5), pmcr);
2342 - mt753x_reg_write(priv, PMCR_REG(6), pmcr);
2343 -}
2344 -
2345 -static int mt7531_setup(struct mtk_eth_priv *priv)
2346 -{
2347 - u16 phy_addr, phy_val;
2348 - u32 val;
2349 - u32 pmcr;
2350 - u32 port5_sgmii;
2351 - int i;
2352 -
2353 - priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
2354 - MT753X_SMI_ADDR_MASK;
2355 -
2356 - /* Turn off PHYs */
2357 - for (i = 0; i < MT753X_NUM_PHYS; i++) {
2358 - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
2359 - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
2360 - phy_val |= BMCR_PDOWN;
2361 - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
2362 - }
2363 -
2364 - /* Force MAC link down before reset */
2365 - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
2366 - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
2367 -
2368 - /* Switch soft reset */
2369 - mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
2370 - udelay(100);
2371 -
2372 - /* Enable MDC input Schmitt Trigger */
2373 - mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN,
2374 - SMT_IOLB_5_SMI_MDC_EN);
2375 -
2376 - mt7531_core_pll_setup(priv, priv->mcm);
2377 -
2378 - mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val);
2379 - port5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
2380 -
2381 - /* port5 support either RGMII or SGMII, port6 only support SGMII. */
2382 - switch (priv->phy_interface) {
2383 - case PHY_INTERFACE_MODE_RGMII:
2384 - if (!port5_sgmii)
2385 - mt7531_port_rgmii_init(priv, 5);
2386 - break;
2387 - case PHY_INTERFACE_MODE_2500BASEX:
2388 - mt7531_port_sgmii_init(priv, 6);
2389 - if (port5_sgmii)
2390 - mt7531_port_sgmii_init(priv, 5);
2391 - break;
2392 - default:
2393 - break;
2394 - }
2395 -
2396 - pmcr = MT7531_FORCE_MODE |
2397 - (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
2398 - MAC_MODE | MAC_TX_EN | MAC_RX_EN |
2399 - BKOFF_EN | BACKPR_EN |
2400 - FORCE_RX_FC | FORCE_TX_FC |
2401 - (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
2402 - FORCE_LINK;
2403 -
2404 - priv->mt753x_pmcr = pmcr;
2405 -
2406 - /* Keep MAC link down before starting eth */
2407 - mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK);
2408 - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
2409 -
2410 - /* Turn on PHYs */
2411 - for (i = 0; i < MT753X_NUM_PHYS; i++) {
2412 - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
2413 - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
2414 - phy_val &= ~BMCR_PDOWN;
2415 - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
2416 - }
2417 -
2418 - mt7531_phy_setting(priv);
2419 -
2420 - /* Enable Internal PHYs */
2421 - val = mt753x_core_reg_read(priv, CORE_PLL_GROUP4);
2422 - val |= MT7531_BYPASS_MODE;
2423 - val &= ~MT7531_POWER_ON_OFF;
2424 - mt753x_core_reg_write(priv, CORE_PLL_GROUP4, val);
2425 -
2426 - return 0;
2427 -}
2428 -
2429 -static void mt7988_phy_setting(struct mtk_eth_priv *priv)
2430 -{
2431 - u16 val;
2432 - u32 i;
2433 -
2434 - for (i = 0; i < MT753X_NUM_PHYS; i++) {
2435 - /* Enable HW auto downshift */
2436 - priv->mii_write(priv, i, 0x1f, 0x1);
2437 - val = priv->mii_read(priv, i, PHY_EXT_REG_14);
2438 - val |= PHY_EN_DOWN_SHFIT;
2439 - priv->mii_write(priv, i, PHY_EXT_REG_14, val);
2440 -
2441 - /* PHY link down power saving enable */
2442 - val = priv->mii_read(priv, i, PHY_EXT_REG_17);
2443 - val |= PHY_LINKDOWN_POWER_SAVING_EN;
2444 - priv->mii_write(priv, i, PHY_EXT_REG_17, val);
2445 - }
2446 -}
2447 -
2448 -static void mt7988_mac_control(struct mtk_eth_priv *priv, bool enable)
2449 -{
2450 - u32 pmcr = FORCE_MODE_LNK;
2451 -
2452 - if (enable)
2453 - pmcr = priv->mt753x_pmcr;
2454 -
2455 - mt753x_reg_write(priv, PMCR_REG(6), pmcr);
2456 -}
2457 -
2458 -static int mt7988_setup(struct mtk_eth_priv *priv)
2459 -{
2460 - u16 phy_addr, phy_val;
2461 - u32 pmcr;
2462 - int i;
2463 -
2464 - priv->gsw_base = regmap_get_range(priv->ethsys_regmap, 0) + GSW_BASE;
2465 -
2466 - priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) &
2467 - MT753X_SMI_ADDR_MASK;
2468 -
2469 - /* Turn off PHYs */
2470 - for (i = 0; i < MT753X_NUM_PHYS; i++) {
2471 - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
2472 - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
2473 - phy_val |= BMCR_PDOWN;
2474 - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
2475 - }
2476 -
2477 - switch (priv->phy_interface) {
2478 - case PHY_INTERFACE_MODE_USXGMII:
2479 - /* Use CPU bridge instead of actual USXGMII path */
2480 -
2481 - /* Set GDM1 no drop */
2482 - mtk_fe_rmw(priv, PSE_NO_DROP_CFG_REG, 0, PSE_NO_DROP_GDM1);
2483 -
2484 - /* Enable GDM1 to GSW CPU bridge */
2485 - mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, BIT(0));
2486 -
2487 - /* XGMAC force link up */
2488 - mtk_gmac_rmw(priv, GMAC_XGMAC_STS_REG, 0, P1_XGMAC_FORCE_LINK);
2489 -
2490 - /* Setup GSW CPU bridge IPG */
2491 - mtk_gmac_rmw(priv, GMAC_GSW_CFG_REG, GSWTX_IPG_M | GSWRX_IPG_M,
2492 - (0xB << GSWTX_IPG_S) | (0xB << GSWRX_IPG_S));
2493 - break;
2494 - default:
2495 - printf("Error: MT7988 GSW does not support %s interface\n",
2496 - phy_string_for_interface(priv->phy_interface));
2497 - break;
2498 - }
2499 -
2500 - pmcr = MT7988_FORCE_MODE |
2501 - (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
2502 - MAC_MODE | MAC_TX_EN | MAC_RX_EN |
2503 - BKOFF_EN | BACKPR_EN |
2504 - FORCE_RX_FC | FORCE_TX_FC |
2505 - (SPEED_1000M << FORCE_SPD_S) | FORCE_DPX |
2506 - FORCE_LINK;
2507 -
2508 - priv->mt753x_pmcr = pmcr;
2509 -
2510 - /* Keep MAC link down before starting eth */
2511 - mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK);
2512 -
2513 - /* Turn on PHYs */
2514 - for (i = 0; i < MT753X_NUM_PHYS; i++) {
2515 - phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i);
2516 - phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
2517 - phy_val &= ~BMCR_PDOWN;
2518 - priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
2519 - }
2520 -
2521 - mt7988_phy_setting(priv);
2522 -
2523 - return 0;
2524 -}
2525 -
2526 -static int mt753x_switch_init(struct mtk_eth_priv *priv)
2527 -{
2528 - int ret;
2529 - int i;
2530 -
2531 - /* Global reset switch */
2532 - if (priv->mcm) {
2533 - reset_assert(&priv->rst_mcm);
2534 - udelay(1000);
2535 - reset_deassert(&priv->rst_mcm);
2536 - mdelay(priv->mt753x_reset_wait_time);
2537 - } else if (dm_gpio_is_valid(&priv->rst_gpio)) {
2538 - dm_gpio_set_value(&priv->rst_gpio, 0);
2539 - udelay(1000);
2540 - dm_gpio_set_value(&priv->rst_gpio, 1);
2541 - mdelay(priv->mt753x_reset_wait_time);
2542 - }
2543 -
2544 - ret = priv->switch_init(priv);
2545 - if (ret)
2546 - return ret;
2547 -
2548 - /* Set port isolation */
2549 - for (i = 0; i < MT753X_NUM_PORTS; i++) {
2550 - /* Set port matrix mode */
2551 - if (i != 6)
2552 - mt753x_reg_write(priv, PCR_REG(i),
2553 - (0x40 << PORT_MATRIX_S));
2554 - else
2555 - mt753x_reg_write(priv, PCR_REG(i),
2556 - (0x3f << PORT_MATRIX_S));
2557 -
2558 - /* Set port mode to user port */
2559 - mt753x_reg_write(priv, PVC_REG(i),
2560 - (0x8100 << STAG_VPID_S) |
2561 - (VLAN_ATTR_USER << VLAN_ATTR_S));
2562 - }
2563 -
2564 - return 0;
2565 -}
2566 -
2567 -static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv)
2568 -{
2569 - u16 lcl_adv = 0, rmt_adv = 0;
2570 - u8 flowctrl;
2571 - u32 mcr;
2572 -
2573 - mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id));
2574 - mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC);
2575 -
2576 - if (priv->phydev->duplex) {
2577 - if (priv->phydev->pause)
2578 - rmt_adv = LPA_PAUSE_CAP;
2579 - if (priv->phydev->asym_pause)
2580 - rmt_adv |= LPA_PAUSE_ASYM;
2581 -
2582 - if (priv->phydev->advertising & ADVERTISED_Pause)
2583 - lcl_adv |= ADVERTISE_PAUSE_CAP;
2584 - if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
2585 - lcl_adv |= ADVERTISE_PAUSE_ASYM;
2586 -
2587 - flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
2588 -
2589 - if (flowctrl & FLOW_CTRL_TX)
2590 - mcr |= XGMAC_FORCE_TX_FC;
2591 - if (flowctrl & FLOW_CTRL_RX)
2592 - mcr |= XGMAC_FORCE_RX_FC;
2593 -
2594 - debug("rx pause %s, tx pause %s\n",
2595 - flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
2596 - flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
2597 - }
2598 -
2599 - mcr &= ~(XGMAC_TRX_DISABLE);
2600 - mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr);
2601 -}
2602 -
2603 -static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
2604 -{
2605 - u16 lcl_adv = 0, rmt_adv = 0;
2606 - u8 flowctrl;
2607 - u32 mcr;
2608 -
2609 - mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
2610 - (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
2611 - MAC_MODE | FORCE_MODE |
2612 - MAC_TX_EN | MAC_RX_EN |
2613 - DEL_RXFIFO_CLR |
2614 - BKOFF_EN | BACKPR_EN;
2615 -
2616 - switch (priv->phydev->speed) {
2617 - case SPEED_10:
2618 - mcr |= (SPEED_10M << FORCE_SPD_S);
2619 - break;
2620 - case SPEED_100:
2621 - mcr |= (SPEED_100M << FORCE_SPD_S);
2622 - break;
2623 - case SPEED_1000:
2624 - case SPEED_2500:
2625 - mcr |= (SPEED_1000M << FORCE_SPD_S);
2626 - break;
2627 - };
2628 -
2629 - if (priv->phydev->link)
2630 - mcr |= FORCE_LINK;
2631 -
2632 - if (priv->phydev->duplex) {
2633 - mcr |= FORCE_DPX;
2634 -
2635 - if (priv->phydev->pause)
2636 - rmt_adv = LPA_PAUSE_CAP;
2637 - if (priv->phydev->asym_pause)
2638 - rmt_adv |= LPA_PAUSE_ASYM;
2639 -
2640 - if (priv->phydev->advertising & ADVERTISED_Pause)
2641 - lcl_adv |= ADVERTISE_PAUSE_CAP;
2642 - if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
2643 - lcl_adv |= ADVERTISE_PAUSE_ASYM;
2644 -
2645 - flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
2646 -
2647 - if (flowctrl & FLOW_CTRL_TX)
2648 - mcr |= FORCE_TX_FC;
2649 - if (flowctrl & FLOW_CTRL_RX)
2650 - mcr |= FORCE_RX_FC;
2651 -
2652 - debug("rx pause %s, tx pause %s\n",
2653 - flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
2654 - flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
2655 - }
2656 -
2657 - mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
2658 -}
2659 -
2660 -static int mtk_phy_start(struct mtk_eth_priv *priv)
2661 -{
2662 - struct phy_device *phydev = priv->phydev;
2663 - int ret;
2664 -
2665 - ret = phy_startup(phydev);
2666 -
2667 - if (ret) {
2668 - debug("Could not initialize PHY %s\n", phydev->dev->name);
2669 - return ret;
2670 - }
2671 -
2672 - if (!phydev->link) {
2673 - debug("%s: link down.\n", phydev->dev->name);
2674 - return 0;
2675 - }
2676 -
2677 - if (!priv->force_mode) {
2678 - if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
2679 - priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
2680 - priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
2681 - mtk_xphy_link_adjust(priv);
2682 - else
2683 - mtk_phy_link_adjust(priv);
2684 - }
2685 -
2686 - debug("Speed: %d, %s duplex%s\n", phydev->speed,
2687 - (phydev->duplex) ? "full" : "half",
2688 - (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
2689 -
2690 - return 0;
2691 -}
2692 -
2693 -static int mtk_phy_probe(struct udevice *dev)
2694 -{
2695 - struct mtk_eth_priv *priv = dev_get_priv(dev);
2696 - struct phy_device *phydev;
2697 -
2698 - phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev,
2699 - priv->phy_interface);
2700 - if (!phydev)
2701 - return -ENODEV;
2702 -
2703 - phydev->supported &= PHY_GBIT_FEATURES;
2704 - phydev->advertising = phydev->supported;
2705 -
2706 - priv->phydev = phydev;
2707 - phy_config(phydev);
2708 -
2709 - return 0;
2710 -}
2711 -
2712 -static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
2713 -{
2714 - /* Set SGMII GEN1 speed(1G) */
2715 - clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK);
2716 -
2717 - /* Enable SGMII AN */
2718 - setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
2719 - SGMII_AN_ENABLE);
2720 -
2721 - /* SGMII AN mode setting */
2722 - writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
2723 -
2724 - /* SGMII PN SWAP setting */
2725 - if (priv->pn_swap) {
2726 - setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
2727 - SGMII_PN_SWAP_TX_RX);
2728 - }
2729 -
2730 - /* Release PHYA power down state */
2731 - clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
2732 - SGMII_PHYA_PWD, 0);
2733 -}
2734 -
2735 -static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
2736 -{
2737 - /* Set SGMII GEN2 speed(2.5G) */
2738 - clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
2739 - SGMSYS_SPEED_MASK,
2740 - FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500));
2741 -
2742 - /* Disable SGMII AN */
2743 - clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
2744 - SGMII_AN_ENABLE, 0);
2745 -
2746 - /* SGMII force mode setting */
2747 - writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
2748 -
2749 - /* SGMII PN SWAP setting */
2750 - if (priv->pn_swap) {
2751 - setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
2752 - SGMII_PN_SWAP_TX_RX);
2753 - }
2754 -
2755 - /* Release PHYA power down state */
2756 - clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
2757 - SGMII_PHYA_PWD, 0);
2758 -}
2759 -
2760 -static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv)
2761 -{
2762 - u32 val = 0;
2763 -
2764 - /* Add software workaround for USXGMII PLL TCL issue */
2765 - regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8,
2766 - RG_XFI_PLL_ANA_SWWA);
2767 -
2768 - regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val);
2769 - val |= RG_XFI_PLL_EN;
2770 - regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val);
2771 -}
2772 -
2773 -static void mtk_usxgmii_reset(struct mtk_eth_priv *priv)
2774 -{
2775 - switch (priv->gmac_id) {
2776 - case 1:
2777 - regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004);
2778 - regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004);
2779 - regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
2780 - regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
2781 - regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
2782 - break;
2783 - case 2:
2784 - regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002);
2785 - regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002);
2786 - regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
2787 - regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
2788 - regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
2789 - break;
2790 - }
2791 -
2792 - mdelay(10);
2793 -}
2794 -
2795 -static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv)
2796 -{
2797 - regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D);
2798 - regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
2799 - regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000);
2800 - ndelay(1020);
2801 - regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000);
2802 - ndelay(1020);
2803 - regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000);
2804 -
2805 - regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
2806 - regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
2807 - regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
2808 - regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
2809 - regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
2810 - regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
2811 - regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
2812 - regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
2813 - regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
2814 - regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
2815 - regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
2816 - regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
2817 - regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
2818 - regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
2819 - regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
2820 - regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
2821 - regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
2822 - regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
2823 - regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
2824 - regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
2825 - regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
2826 - regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
2827 - regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
2828 - regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
2829 - ndelay(1020);
2830 - regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
2831 - regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
2832 - regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
2833 - regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
2834 - regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
2835 - regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
2836 - regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
2837 - regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000);
2838 - regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000);
2839 - regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA);
2840 - regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
2841 - regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
2842 - regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
2843 - regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
2844 - udelay(150);
2845 - regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
2846 - ndelay(1020);
2847 - regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
2848 - udelay(15);
2849 - regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
2850 - ndelay(1020);
2851 - regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
2852 - udelay(100);
2853 - regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
2854 - regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
2855 - regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
2856 - udelay(400);
2857 -}
2858 -
2859 -static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv)
2860 -{
2861 - regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C);
2862 - regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
2863 - regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000);
2864 - ndelay(1020);
2865 - regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000);
2866 - ndelay(1020);
2867 -
2868 - regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
2869 - regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
2870 - regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
2871 - regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
2872 - regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
2873 - regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
2874 - regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
2875 - regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
2876 - regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
2877 - regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
2878 - regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
2879 - regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
2880 - regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
2881 - regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
2882 - regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
2883 - regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
2884 - regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
2885 - regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
2886 - regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
2887 - regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
2888 - regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
2889 - regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
2890 - regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
2891 - regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
2892 - ndelay(1020);
2893 - regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
2894 - regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
2895 - regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
2896 - regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
2897 - regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
2898 - regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
2899 - regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
2900 - regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100);
2901 - regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000);
2902 - regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000);
2903 - regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
2904 - if (priv->gmac_id == 2)
2905 - regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400);
2906 - regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
2907 - regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
2908 - regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
2909 - udelay(150);
2910 - regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
2911 - ndelay(1020);
2912 - regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
2913 - udelay(15);
2914 - regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
2915 - ndelay(1020);
2916 - regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
2917 - udelay(100);
2918 - regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
2919 - regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
2920 - regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
2921 - udelay(400);
2922 -}
2923 -
2924 -static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
2925 -{
2926 - mtk_xfi_pll_enable(priv);
2927 - mtk_usxgmii_reset(priv);
2928 - mtk_usxgmii_setup_phya_an_10000(priv);
2929 -}
2930 -
2931 -static void mtk_10gbaser_init(struct mtk_eth_priv *priv)
2932 -{
2933 - mtk_xfi_pll_enable(priv);
2934 - mtk_usxgmii_reset(priv);
2935 - mtk_usxgmii_setup_phya_force_10000(priv);
2936 -}
2937 -
2938 -static int mtk_mac_init(struct mtk_eth_priv *priv)
2939 -{
2940 - int i, sgmii_sel_mask = 0, ge_mode = 0;
2941 - u32 mcr;
2942 -
2943 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) {
2944 - mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG,
2945 - INFRA_MISC2_BONDING_OPTION, priv->gmac_id);
2946 - }
2947 -
2948 - switch (priv->phy_interface) {
2949 - case PHY_INTERFACE_MODE_RGMII_RXID:
2950 - case PHY_INTERFACE_MODE_RGMII:
2951 - ge_mode = GE_MODE_RGMII;
2952 - break;
2953 - case PHY_INTERFACE_MODE_SGMII:
2954 - case PHY_INTERFACE_MODE_2500BASEX:
2955 - if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) {
2956 - printf("Error: SGMII is not supported on this platform\n");
2957 - return -ENOTSUPP;
2958 - }
2959 -
2960 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) {
2961 - mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK,
2962 - SGMII_QPHY_SEL);
2963 - }
2964 -
2965 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII))
2966 - sgmii_sel_mask = SYSCFG1_SGMII_SEL_M;
2967 -
2968 - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask,
2969 - SYSCFG1_SGMII_SEL(priv->gmac_id));
2970 -
2971 - if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
2972 - mtk_sgmii_an_init(priv);
2973 - else
2974 - mtk_sgmii_force_init(priv);
2975 -
2976 - ge_mode = GE_MODE_RGMII;
2977 - break;
2978 - case PHY_INTERFACE_MODE_MII:
2979 - case PHY_INTERFACE_MODE_GMII:
2980 - ge_mode = GE_MODE_MII;
2981 - break;
2982 - case PHY_INTERFACE_MODE_RMII:
2983 - ge_mode = GE_MODE_RMII;
2984 - break;
2985 - default:
2986 - break;
2987 - }
2988 -
2989 - /* set the gmac to the right mode */
2990 - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG,
2991 - SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
2992 - ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id));
2993 -
2994 - if (priv->force_mode) {
2995 - mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
2996 - (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
2997 - MAC_MODE | FORCE_MODE |
2998 - MAC_TX_EN | MAC_RX_EN |
2999 - BKOFF_EN | BACKPR_EN |
3000 - FORCE_LINK;
3001 -
3002 - switch (priv->speed) {
3003 - case SPEED_10:
3004 - mcr |= SPEED_10M << FORCE_SPD_S;
3005 - break;
3006 - case SPEED_100:
3007 - mcr |= SPEED_100M << FORCE_SPD_S;
3008 - break;
3009 - case SPEED_1000:
3010 - case SPEED_2500:
3011 - mcr |= SPEED_1000M << FORCE_SPD_S;
3012 - break;
3013 - }
3014 -
3015 - if (priv->duplex)
3016 - mcr |= FORCE_DPX;
3017 -
3018 - mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
3019 - }
3020 -
3021 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC1_TRGMII) &&
3022 - !MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) {
3023 - /* Lower Tx Driving for TRGMII path */
3024 - for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
3025 - mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i),
3026 - (8 << TD_DM_DRVP_S) |
3027 - (8 << TD_DM_DRVN_S));
3028 -
3029 - mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0,
3030 - RX_RST | RXC_DQSISEL);
3031 - mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0);
3032 - }
3033 -
3034 - return 0;
3035 -}
3036 -
3037 -static int mtk_xmac_init(struct mtk_eth_priv *priv)
3038 -{
3039 - u32 force_link = 0;
3040 -
3041 - if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) {
3042 - printf("Error: 10Gb interface is not supported on this platform\n");
3043 - return -ENOTSUPP;
3044 - }
3045 -
3046 - switch (priv->phy_interface) {
3047 - case PHY_INTERFACE_MODE_USXGMII:
3048 - mtk_usxgmii_an_init(priv);
3049 - break;
3050 - case PHY_INTERFACE_MODE_10GBASER:
3051 - mtk_10gbaser_init(priv);
3052 - break;
3053 - default:
3054 - break;
3055 - }
3056 -
3057 - /* Set GMAC to the correct mode */
3058 - mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG,
3059 - SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
3060 - 0);
3061 -
3062 - if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
3063 - priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) &&
3064 - priv->gmac_id == 1) {
3065 - mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
3066 - NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
3067 - }
3068 -
3069 - if (priv->phy_interface == PHY_INTERFACE_MODE_XGMII ||
3070 - priv->gmac_id == 2)
3071 - force_link = XGMAC_FORCE_LINK(priv->gmac_id);
3072 -
3073 - mtk_gmac_rmw(priv, XGMAC_STS(priv->gmac_id),
3074 - XGMAC_FORCE_LINK(priv->gmac_id), force_link);
3075 -
3076 - /* Force GMAC link down */
3077 - mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
3078 -
3079 - return 0;
3080 -}
3081 -
3082 -static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
3083 -{
3084 - char *pkt_base = priv->pkt_pool;
3085 - struct mtk_tx_dma_v2 *txd;
3086 - struct mtk_rx_dma_v2 *rxd;
3087 - int i;
3088 -
3089 - mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0);
3090 - udelay(500);
3091 -
3092 - memset(priv->tx_ring_noc, 0, NUM_TX_DESC * priv->soc->txd_size);
3093 - memset(priv->rx_ring_noc, 0, NUM_RX_DESC * priv->soc->rxd_size);
3094 - memset(priv->pkt_pool, 0xff, TOTAL_PKT_BUF_SIZE);
3095 -
3096 - flush_dcache_range((ulong)pkt_base,
3097 - (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE));
3098 -
3099 - priv->rx_dma_owner_idx0 = 0;
3100 - priv->tx_cpu_owner_idx0 = 0;
3101 -
3102 - for (i = 0; i < NUM_TX_DESC; i++) {
3103 - txd = priv->tx_ring_noc + i * priv->soc->txd_size;
3104 -
3105 - txd->txd1 = virt_to_phys(pkt_base);
3106 - txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0;
3107 -
3108 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
3109 - txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ?
3110 - 15 : priv->gmac_id + 1);
3111 - else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
3112 - txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1);
3113 - else
3114 - txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1);
3115 -
3116 - pkt_base += PKTSIZE_ALIGN;
3117 - }
3118 -
3119 - for (i = 0; i < NUM_RX_DESC; i++) {
3120 - rxd = priv->rx_ring_noc + i * priv->soc->rxd_size;
3121 -
3122 - rxd->rxd1 = virt_to_phys(pkt_base);
3123 -
3124 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
3125 - MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
3126 - rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
3127 - else
3128 - rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
3129 -
3130 - pkt_base += PKTSIZE_ALIGN;
3131 - }
3132 -
3133 - mtk_pdma_write(priv, TX_BASE_PTR_REG(0),
3134 - virt_to_phys(priv->tx_ring_noc));
3135 - mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC);
3136 - mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
3137 -
3138 - mtk_pdma_write(priv, RX_BASE_PTR_REG(0),
3139 - virt_to_phys(priv->rx_ring_noc));
3140 - mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC);
3141 - mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1);
3142 -
3143 - mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0);
3144 -}
3145 -
3146 -static void mtk_eth_mdc_init(struct mtk_eth_priv *priv)
3147 -{
3148 - u32 divider;
3149 -
3150 - if (priv->mdc == 0)
3151 - return;
3152 -
3153 - divider = min_t(u32, DIV_ROUND_UP(MDC_MAX_FREQ, priv->mdc), MDC_MAX_DIVIDER);
3154 -
3155 - /* Configure MDC turbo mode */
3156 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
3157 - mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, MISC_MDC_TURBO);
3158 - else
3159 - mtk_gmac_rmw(priv, GMAC_PPSC_REG, 0, MISC_MDC_TURBO);
3160 -
3161 - /* Configure MDC divider */
3162 - mtk_gmac_rmw(priv, GMAC_PPSC_REG, PHY_MDC_CFG,
3163 - FIELD_PREP(PHY_MDC_CFG, divider));
3164 -}
3165 -
3166 -static int mtk_eth_start(struct udevice *dev)
3167 -{
3168 - struct mtk_eth_priv *priv = dev_get_priv(dev);
3169 - int i, ret;
3170 -
3171 - /* Reset FE */
3172 - reset_assert(&priv->rst_fe);
3173 - udelay(1000);
3174 - reset_deassert(&priv->rst_fe);
3175 - mdelay(10);
3176 -
3177 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
3178 - MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
3179 - setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2);
3180 -
3181 - /* Packets forward to PDMA */
3182 - mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
3183 -
3184 - for (i = 0; i < priv->soc->gdma_count; i++) {
3185 - if (i == priv->gmac_id)
3186 - continue;
3187 -
3188 - mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
3189 - }
3190 -
3191 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
3192 - if (priv->sw == SW_MT7988 && priv->gmac_id == 0) {
3193 - mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG,
3194 - GDMA_BRIDGE_TO_CPU);
3195 -
3196 - mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
3197 - GDMA_CPU_BRIDGE_EN);
3198 - } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
3199 - priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
3200 - priv->phy_interface == PHY_INTERFACE_MODE_XGMII) &&
3201 - priv->gmac_id != 0) {
3202 - mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
3203 - GDMA_CPU_BRIDGE_EN);
3204 - }
3205 - }
3206 -
3207 - udelay(500);
3208 -
3209 - mtk_eth_fifo_init(priv);
3210 -
3211 - if (priv->switch_mac_control)
3212 - priv->switch_mac_control(priv, true);
3213 -
3214 - /* Start PHY */
3215 - if (priv->sw == SW_NONE) {
3216 - ret = mtk_phy_start(priv);
3217 - if (ret)
3218 - return ret;
3219 - }
3220 -
3221 - mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0,
3222 - TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
3223 - udelay(500);
3224 -
3225 - return 0;
3226 -}
3227 -
3228 -static void mtk_eth_stop(struct udevice *dev)
3229 -{
3230 - struct mtk_eth_priv *priv = dev_get_priv(dev);
3231 -
3232 - if (priv->switch_mac_control)
3233 - priv->switch_mac_control(priv, false);
3234 -
3235 - mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
3236 - TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
3237 - udelay(500);
3238 -
3239 - wait_for_bit_le32(priv->fe_base + priv->soc->pdma_base + PDMA_GLO_CFG_REG,
3240 - RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0);
3241 -}
3242 -
3243 -static int mtk_eth_write_hwaddr(struct udevice *dev)
3244 -{
3245 - struct eth_pdata *pdata = dev_get_plat(dev);
3246 - struct mtk_eth_priv *priv = dev_get_priv(dev);
3247 - unsigned char *mac = pdata->enetaddr;
3248 - u32 macaddr_lsb, macaddr_msb;
3249 -
3250 - macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1];
3251 - macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) |
3252 - ((u32)mac[4] << 8) | (u32)mac[5];
3253 -
3254 - mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb);
3255 - mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb);
3256 -
3257 - return 0;
3258 -}
3259 -
3260 -static int mtk_eth_send(struct udevice *dev, void *packet, int length)
3261 -{
3262 - struct mtk_eth_priv *priv = dev_get_priv(dev);
3263 - u32 idx = priv->tx_cpu_owner_idx0;
3264 - struct mtk_tx_dma_v2 *txd;
3265 - void *pkt_base;
3266 -
3267 - txd = priv->tx_ring_noc + idx * priv->soc->txd_size;
3268 -
3269 - if (!(txd->txd2 & PDMA_TXD2_DDONE)) {
3270 - debug("mtk-eth: TX DMA descriptor ring is full\n");
3271 - return -EPERM;
3272 - }
3273 -
3274 - pkt_base = (void *)phys_to_virt(txd->txd1);
3275 - memcpy(pkt_base, packet, length);
3276 - flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
3277 - roundup(length, ARCH_DMA_MINALIGN));
3278 -
3279 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
3280 - MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
3281 - txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length);
3282 - else
3283 - txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length);
3284 -
3285 - priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC;
3286 - mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
3287 -
3288 - return 0;
3289 -}
3290 -
3291 -static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp)
3292 -{
3293 - struct mtk_eth_priv *priv = dev_get_priv(dev);
3294 - u32 idx = priv->rx_dma_owner_idx0;
3295 - struct mtk_rx_dma_v2 *rxd;
3296 - uchar *pkt_base;
3297 - u32 length;
3298 -
3299 - rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
3300 -
3301 - if (!(rxd->rxd2 & PDMA_RXD2_DDONE)) {
3302 - debug("mtk-eth: RX DMA descriptor ring is empty\n");
3303 - return -EAGAIN;
3304 - }
3305 -
3306 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
3307 - MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
3308 - length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2);
3309 - else
3310 - length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2);
3311 -
3312 - pkt_base = (void *)phys_to_virt(rxd->rxd1);
3313 - invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base +
3314 - roundup(length, ARCH_DMA_MINALIGN));
3315 -
3316 - if (packetp)
3317 - *packetp = pkt_base;
3318 -
3319 - return length;
3320 -}
3321 -
3322 -static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
3323 -{
3324 - struct mtk_eth_priv *priv = dev_get_priv(dev);
3325 - u32 idx = priv->rx_dma_owner_idx0;
3326 - struct mtk_rx_dma_v2 *rxd;
3327 -
3328 - rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
3329 -
3330 - invalidate_dcache_range((ulong)rxd->rxd1,
3331 - (ulong)rxd->rxd1 + PKTSIZE_ALIGN);
3332 -
3333 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
3334 - MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
3335 - rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
3336 - else
3337 - rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
3338 -
3339 - mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx);
3340 - priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC;
3341 -
3342 - return 0;
3343 -}
3344 -
3345 -static int mtk_eth_probe(struct udevice *dev)
3346 -{
3347 - struct eth_pdata *pdata = dev_get_plat(dev);
3348 - struct mtk_eth_priv *priv = dev_get_priv(dev);
3349 - ulong iobase = pdata->iobase;
3350 - int ret;
3351 -
3352 - /* Frame Engine Register Base */
3353 - priv->fe_base = (void *)iobase;
3354 -
3355 - /* GMAC Register Base */
3356 - priv->gmac_base = (void *)(iobase + GMAC_BASE);
3357 -
3358 - /* MDIO register */
3359 - ret = mtk_mdio_register(dev);
3360 - if (ret)
3361 - return ret;
3362 -
3363 - /* Prepare for tx/rx rings */
3364 - priv->tx_ring_noc = (void *)
3365 - noncached_alloc(priv->soc->txd_size * NUM_TX_DESC,
3366 - ARCH_DMA_MINALIGN);
3367 - priv->rx_ring_noc = (void *)
3368 - noncached_alloc(priv->soc->rxd_size * NUM_RX_DESC,
3369 - ARCH_DMA_MINALIGN);
3370 -
3371 - /* Set MDC divider */
3372 - mtk_eth_mdc_init(priv);
3373 -
3374 - /* Set MAC mode */
3375 - if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
3376 - priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
3377 - priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
3378 - ret = mtk_xmac_init(priv);
3379 - else
3380 - ret = mtk_mac_init(priv);
3381 -
3382 - if (ret)
3383 - return ret;
3384 -
3385 - /* Probe phy if switch is not specified */
3386 - if (priv->sw == SW_NONE)
3387 - return mtk_phy_probe(dev);
3388 -
3389 - /* Initialize switch */
3390 - return mt753x_switch_init(priv);
3391 -}
3392 -
3393 -static int mtk_eth_remove(struct udevice *dev)
3394 -{
3395 - struct mtk_eth_priv *priv = dev_get_priv(dev);
3396 -
3397 - /* MDIO unregister */
3398 - mdio_unregister(priv->mdio_bus);
3399 - mdio_free(priv->mdio_bus);
3400 -
3401 - /* Stop possibly started DMA */
3402 - mtk_eth_stop(dev);
3403 -
3404 - return 0;
3405 -}
3406 -
3407 -static int mtk_eth_of_to_plat(struct udevice *dev)
3408 -{
3409 - struct eth_pdata *pdata = dev_get_plat(dev);
3410 - struct mtk_eth_priv *priv = dev_get_priv(dev);
3411 - struct ofnode_phandle_args args;
3412 - struct regmap *regmap;
3413 - const char *str;
3414 - ofnode subnode;
3415 - int ret;
3416 -
3417 - priv->soc = (const struct mtk_soc_data *)dev_get_driver_data(dev);
3418 - if (!priv->soc) {
3419 - dev_err(dev, "missing soc compatible data\n");
3420 - return -EINVAL;
3421 - }
3422 -
3423 - pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
3424 -
3425 - /* get corresponding ethsys phandle */
3426 - ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0,
3427 - &args);
3428 - if (ret)
3429 - return ret;
3430 -
3431 - priv->ethsys_regmap = syscon_node_to_regmap(args.node);
3432 - if (IS_ERR(priv->ethsys_regmap))
3433 - return PTR_ERR(priv->ethsys_regmap);
3434 -
3435 - if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) {
3436 - /* get corresponding infracfg phandle */
3437 - ret = dev_read_phandle_with_args(dev, "mediatek,infracfg",
3438 - NULL, 0, 0, &args);
3439 -
3440 - if (ret)
3441 - return ret;
3442 -
3443 - priv->infra_regmap = syscon_node_to_regmap(args.node);
3444 - if (IS_ERR(priv->infra_regmap))
3445 - return PTR_ERR(priv->infra_regmap);
3446 - }
3447 -
3448 - /* Reset controllers */
3449 - ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
3450 - if (ret) {
3451 - printf("error: Unable to get reset ctrl for frame engine\n");
3452 - return ret;
3453 - }
3454 -
3455 - priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0);
3456 -
3457 - priv->mdc = 0;
3458 - subnode = ofnode_find_subnode(dev_ofnode(dev), "mdio");
3459 - if (ofnode_valid(subnode)) {
3460 - priv->mdc = ofnode_read_u32_default(subnode, "clock-frequency", 2500000);
3461 - if (priv->mdc > MDC_MAX_FREQ ||
3462 - priv->mdc < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
3463 - printf("error: MDIO clock frequency out of range\n");
3464 - return -EINVAL;
3465 - }
3466 - }
3467 -
3468 - /* Interface mode is required */
3469 - pdata->phy_interface = dev_read_phy_mode(dev);
3470 - priv->phy_interface = pdata->phy_interface;
3471 - if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
3472 - printf("error: phy-mode is not set\n");
3473 - return -EINVAL;
3474 - }
3475 -
3476 - /* Force mode or autoneg */
3477 - subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link");
3478 - if (ofnode_valid(subnode)) {
3479 - priv->force_mode = 1;
3480 - priv->speed = ofnode_read_u32_default(subnode, "speed", 0);
3481 - priv->duplex = ofnode_read_bool(subnode, "full-duplex");
3482 -
3483 - if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
3484 - priv->speed != SPEED_1000 && priv->speed != SPEED_2500 &&
3485 - priv->speed != SPEED_10000) {
3486 - printf("error: no valid speed set in fixed-link\n");
3487 - return -EINVAL;
3488 - }
3489 - }
3490 -
3491 - if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
3492 - priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) &&
3493 - IS_ENABLED(CONFIG_MTK_ETH_SGMII)) {
3494 - /* get corresponding sgmii phandle */
3495 - ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
3496 - NULL, 0, 0, &args);
3497 - if (ret)
3498 - return ret;
3499 -
3500 - regmap = syscon_node_to_regmap(args.node);
3501 -
3502 - if (IS_ERR(regmap))
3503 - return PTR_ERR(regmap);
3504 -
3505 - priv->sgmii_base = regmap_get_range(regmap, 0);
3506 -
3507 - if (!priv->sgmii_base) {
3508 - dev_err(dev, "Unable to find sgmii\n");
3509 - return -ENODEV;
3510 - }
3511 -
3512 - /* Upstream linux use mediatek,pnswap instead of pn_swap */
3513 - priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") ||
3514 - ofnode_read_bool(args.node, "mediatek,pnswap");
3515 - } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
3516 - priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) &&
3517 - IS_ENABLED(CONFIG_MTK_ETH_XGMII)) {
3518 - /* get corresponding usxgmii phandle */
3519 - ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
3520 - NULL, 0, 0, &args);
3521 - if (ret)
3522 - return ret;
3523 -
3524 - priv->usxgmii_regmap = syscon_node_to_regmap(args.node);
3525 - if (IS_ERR(priv->usxgmii_regmap))
3526 - return PTR_ERR(priv->usxgmii_regmap);
3527 -
3528 - /* get corresponding xfi_pextp phandle */
3529 - ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp",
3530 - NULL, 0, 0, &args);
3531 - if (ret)
3532 - return ret;
3533 -
3534 - priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node);
3535 - if (IS_ERR(priv->xfi_pextp_regmap))
3536 - return PTR_ERR(priv->xfi_pextp_regmap);
3537 -
3538 - /* get corresponding xfi_pll phandle */
3539 - ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll",
3540 - NULL, 0, 0, &args);
3541 - if (ret)
3542 - return ret;
3543 -
3544 - priv->xfi_pll_regmap = syscon_node_to_regmap(args.node);
3545 - if (IS_ERR(priv->xfi_pll_regmap))
3546 - return PTR_ERR(priv->xfi_pll_regmap);
3547 -
3548 - /* get corresponding toprgu phandle */
3549 - ret = dev_read_phandle_with_args(dev, "mediatek,toprgu",
3550 - NULL, 0, 0, &args);
3551 - if (ret)
3552 - return ret;
3553 -
3554 - priv->toprgu_regmap = syscon_node_to_regmap(args.node);
3555 - if (IS_ERR(priv->toprgu_regmap))
3556 - return PTR_ERR(priv->toprgu_regmap);
3557 - }
3558 -
3559 - /* check for switch first, otherwise phy will be used */
3560 - priv->sw = SW_NONE;
3561 - priv->switch_init = NULL;
3562 - priv->switch_mac_control = NULL;
3563 - str = dev_read_string(dev, "mediatek,switch");
3564 -
3565 - if (str) {
3566 - if (!strcmp(str, "mt7530")) {
3567 - priv->sw = SW_MT7530;
3568 - priv->switch_init = mt7530_setup;
3569 - priv->switch_mac_control = mt7530_mac_control;
3570 - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
3571 - priv->mt753x_reset_wait_time = 1000;
3572 - } else if (!strcmp(str, "mt7531")) {
3573 - priv->sw = SW_MT7531;
3574 - priv->switch_init = mt7531_setup;
3575 - priv->switch_mac_control = mt7531_mac_control;
3576 - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
3577 - priv->mt753x_reset_wait_time = 200;
3578 - } else if (!strcmp(str, "mt7988")) {
3579 - priv->sw = SW_MT7988;
3580 - priv->switch_init = mt7988_setup;
3581 - priv->switch_mac_control = mt7988_mac_control;
3582 - priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR;
3583 - priv->mt753x_reset_wait_time = 50;
3584 - } else {
3585 - printf("error: unsupported switch\n");
3586 - return -EINVAL;
3587 - }
3588 -
3589 - priv->mcm = dev_read_bool(dev, "mediatek,mcm");
3590 - if (priv->mcm) {
3591 - ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm);
3592 - if (ret) {
3593 - printf("error: no reset ctrl for mcm\n");
3594 - return ret;
3595 - }
3596 - } else {
3597 - gpio_request_by_name(dev, "reset-gpios", 0,
3598 - &priv->rst_gpio, GPIOD_IS_OUT);
3599 - }
3600 - } else {
3601 - ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0,
3602 - 0, &args);
3603 - if (ret) {
3604 - printf("error: phy-handle is not specified\n");
3605 - return ret;
3606 - }
3607 -
3608 - priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1);
3609 - if (priv->phy_addr < 0) {
3610 - printf("error: phy address is not specified\n");
3611 - return ret;
3612 - }
3613 - }
3614 -
3615 - return 0;
3616 -}
3617 -
3618 -static const struct mtk_soc_data mt7988_data = {
3619 - .caps = MT7988_CAPS,
3620 - .ana_rgc3 = 0x128,
3621 - .gdma_count = 3,
3622 - .pdma_base = PDMA_V3_BASE,
3623 - .txd_size = sizeof(struct mtk_tx_dma_v2),
3624 - .rxd_size = sizeof(struct mtk_rx_dma_v2),
3625 -};
3626 -
3627 -static const struct mtk_soc_data mt7986_data = {
3628 - .caps = MT7986_CAPS,
3629 - .ana_rgc3 = 0x128,
3630 - .gdma_count = 2,
3631 - .pdma_base = PDMA_V2_BASE,
3632 - .txd_size = sizeof(struct mtk_tx_dma_v2),
3633 - .rxd_size = sizeof(struct mtk_rx_dma_v2),
3634 -};
3635 -
3636 -static const struct mtk_soc_data mt7981_data = {
3637 - .caps = MT7981_CAPS,
3638 - .ana_rgc3 = 0x128,
3639 - .gdma_count = 2,
3640 - .pdma_base = PDMA_V2_BASE,
3641 - .txd_size = sizeof(struct mtk_tx_dma_v2),
3642 - .rxd_size = sizeof(struct mtk_rx_dma_v2),
3643 -};
3644 -
3645 -static const struct mtk_soc_data mt7629_data = {
3646 - .caps = MT7629_CAPS,
3647 - .ana_rgc3 = 0x128,
3648 - .gdma_count = 2,
3649 - .pdma_base = PDMA_V1_BASE,
3650 - .txd_size = sizeof(struct mtk_tx_dma),
3651 - .rxd_size = sizeof(struct mtk_rx_dma),
3652 -};
3653 -
3654 -static const struct mtk_soc_data mt7623_data = {
3655 - .caps = MT7623_CAPS,
3656 - .gdma_count = 2,
3657 - .pdma_base = PDMA_V1_BASE,
3658 - .txd_size = sizeof(struct mtk_tx_dma),
3659 - .rxd_size = sizeof(struct mtk_rx_dma),
3660 -};
3661 -
3662 -static const struct mtk_soc_data mt7622_data = {
3663 - .caps = MT7622_CAPS,
3664 - .ana_rgc3 = 0x2028,
3665 - .gdma_count = 2,
3666 - .pdma_base = PDMA_V1_BASE,
3667 - .txd_size = sizeof(struct mtk_tx_dma),
3668 - .rxd_size = sizeof(struct mtk_rx_dma),
3669 -};
3670 -
3671 -static const struct mtk_soc_data mt7621_data = {
3672 - .caps = MT7621_CAPS,
3673 - .gdma_count = 2,
3674 - .pdma_base = PDMA_V1_BASE,
3675 - .txd_size = sizeof(struct mtk_tx_dma),
3676 - .rxd_size = sizeof(struct mtk_rx_dma),
3677 -};
3678 -
3679 -static const struct udevice_id mtk_eth_ids[] = {
3680 - { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data },
3681 - { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
3682 - { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
3683 - { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
3684 - { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data },
3685 - { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data },
3686 - { .compatible = "mediatek,mt7621-eth", .data = (ulong)&mt7621_data },
3687 - {}
3688 -};
3689 -
3690 -static const struct eth_ops mtk_eth_ops = {
3691 - .start = mtk_eth_start,
3692 - .stop = mtk_eth_stop,
3693 - .send = mtk_eth_send,
3694 - .recv = mtk_eth_recv,
3695 - .free_pkt = mtk_eth_free_pkt,
3696 - .write_hwaddr = mtk_eth_write_hwaddr,
3697 -};
3698 -
3699 -U_BOOT_DRIVER(mtk_eth) = {
3700 - .name = "mtk-eth",
3701 - .id = UCLASS_ETH,
3702 - .of_match = mtk_eth_ids,
3703 - .of_to_plat = mtk_eth_of_to_plat,
3704 - .plat_auto = sizeof(struct eth_pdata),
3705 - .probe = mtk_eth_probe,
3706 - .remove = mtk_eth_remove,
3707 - .ops = &mtk_eth_ops,
3708 - .priv_auto = sizeof(struct mtk_eth_priv),
3709 - .flags = DM_FLAG_ALLOC_PRIV_DMA,
3710 -};
3711 --- /dev/null
3712 +++ b/drivers/net/mtk_eth/mtk_eth.c
3713 @@ -0,0 +1,1563 @@
3714 +// SPDX-License-Identifier: GPL-2.0
3715 +/*
3716 + * Copyright (C) 2025 MediaTek Inc.
3717 + *
3718 + * Author: Weijie Gao <weijie.gao@mediatek.com>
3719 + * Author: Mark Lee <mark-mc.lee@mediatek.com>
3720 + */
3721 +
3722 +#include <cpu_func.h>
3723 +#include <dm.h>
3724 +#include <log.h>
3725 +#include <malloc.h>
3726 +#include <miiphy.h>
3727 +#include <net.h>
3728 +#include <regmap.h>
3729 +#include <reset.h>
3730 +#include <syscon.h>
3731 +#include <wait_bit.h>
3732 +#include <asm/cache.h>
3733 +#include <asm/gpio.h>
3734 +#include <asm/io.h>
3735 +#include <dm/device_compat.h>
3736 +#include <linux/delay.h>
3737 +#include <linux/err.h>
3738 +#include <linux/ioport.h>
3739 +#include <linux/mdio.h>
3740 +#include <linux/mii.h>
3741 +#include <linux/printk.h>
3742 +
3743 +#include "mtk_eth.h"
3744 +
3745 +#define NUM_TX_DESC 32
3746 +#define NUM_RX_DESC 32
3747 +#define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN)
3748 +#define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN)
3749 +#define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE)
3750 +
3751 +#define GDMA_FWD_TO_CPU \
3752 + (0x20000000 | \
3753 + GDM_ICS_EN | \
3754 + GDM_TCS_EN | \
3755 + GDM_UCS_EN | \
3756 + STRP_CRC | \
3757 + (DP_PDMA << MYMAC_DP_S) | \
3758 + (DP_PDMA << BC_DP_S) | \
3759 + (DP_PDMA << MC_DP_S) | \
3760 + (DP_PDMA << UN_DP_S))
3761 +
3762 +#define GDMA_BRIDGE_TO_CPU \
3763 + (0xC0000000 | \
3764 + GDM_ICS_EN | \
3765 + GDM_TCS_EN | \
3766 + GDM_UCS_EN | \
3767 + (DP_PDMA << MYMAC_DP_S) | \
3768 + (DP_PDMA << BC_DP_S) | \
3769 + (DP_PDMA << MC_DP_S) | \
3770 + (DP_PDMA << UN_DP_S))
3771 +
3772 +#define GDMA_FWD_DISCARD \
3773 + (0x20000000 | \
3774 + GDM_ICS_EN | \
3775 + GDM_TCS_EN | \
3776 + GDM_UCS_EN | \
3777 + STRP_CRC | \
3778 + (DP_DISCARD << MYMAC_DP_S) | \
3779 + (DP_DISCARD << BC_DP_S) | \
3780 + (DP_DISCARD << MC_DP_S) | \
3781 + (DP_DISCARD << UN_DP_S))
3782 +
3783 +struct mtk_eth_priv {
3784 + char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
3785 +
3786 + void *tx_ring_noc;
3787 + void *rx_ring_noc;
3788 +
3789 + int rx_dma_owner_idx0;
3790 + int tx_cpu_owner_idx0;
3791 +
3792 + void __iomem *fe_base;
3793 + void __iomem *gmac_base;
3794 + void __iomem *sgmii_base;
3795 +
3796 + struct regmap *ethsys_regmap;
3797 +
3798 + struct regmap *infra_regmap;
3799 +
3800 + struct regmap *usxgmii_regmap;
3801 + struct regmap *xfi_pextp_regmap;
3802 + struct regmap *xfi_pll_regmap;
3803 + struct regmap *toprgu_regmap;
3804 +
3805 + struct mii_dev *mdio_bus;
3806 +
3807 + const struct mtk_soc_data *soc;
3808 + int gmac_id;
3809 + int force_mode;
3810 + int speed;
3811 + int duplex;
3812 + int mdc;
3813 + bool pn_swap;
3814 +
3815 + struct phy_device *phydev;
3816 + int phy_interface;
3817 + int phy_addr;
3818 +
3819 + struct mtk_eth_switch_priv *swpriv;
3820 + const char *swname;
3821 +
3822 + struct gpio_desc rst_gpio;
3823 + int mcm;
3824 +
3825 + struct reset_ctl rst_fe;
3826 + struct reset_ctl rst_mcm;
3827 +};
3828 +
3829 +static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
3830 +{
3831 + writel(val, priv->fe_base + priv->soc->pdma_base + reg);
3832 +}
3833 +
3834 +static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
3835 + u32 set)
3836 +{
3837 + clrsetbits_le32(priv->fe_base + priv->soc->pdma_base + reg, clr, set);
3838 +}
3839 +
3840 +static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg,
3841 + u32 val)
3842 +{
3843 + u32 gdma_base;
3844 +
3845 + if (no == 2)
3846 + gdma_base = GDMA3_BASE;
3847 + else if (no == 1)
3848 + gdma_base = GDMA2_BASE;
3849 + else
3850 + gdma_base = GDMA1_BASE;
3851 +
3852 + writel(val, priv->fe_base + gdma_base + reg);
3853 +}
3854 +
3855 +void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
3856 +{
3857 + clrsetbits_le32(priv->fe_base + reg, clr, set);
3858 +}
3859 +
3860 +static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
3861 +{
3862 + return readl(priv->gmac_base + reg);
3863 +}
3864 +
3865 +static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
3866 +{
3867 + writel(val, priv->gmac_base + reg);
3868 +}
3869 +
3870 +void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
3871 +{
3872 + clrsetbits_le32(priv->gmac_base + reg, clr, set);
3873 +}
3874 +
3875 +void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
3876 +{
3877 + uint val;
3878 +
3879 + regmap_read(priv->ethsys_regmap, reg, &val);
3880 + val &= ~clr;
3881 + val |= set;
3882 + regmap_write(priv->ethsys_regmap, reg, val);
3883 +}
3884 +
3885 +static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
3886 + u32 set)
3887 +{
3888 + uint val;
3889 +
3890 + regmap_read(priv->infra_regmap, reg, &val);
3891 + val &= ~clr;
3892 + val |= set;
3893 + regmap_write(priv->infra_regmap, reg, val);
3894 +}
3895 +
3896 +/* Direct MDIO clause 22/45 access via SoC */
3897 +static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
3898 + u32 cmd, u32 st)
3899 +{
3900 + int ret;
3901 + u32 val;
3902 +
3903 + val = (st << MDIO_ST_S) |
3904 + ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
3905 + (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
3906 + (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
3907 +
3908 + if (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)
3909 + val |= data & MDIO_RW_DATA_M;
3910 +
3911 + mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
3912 +
3913 + ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG,
3914 + PHY_ACS_ST, 0, 5000, 0);
3915 + if (ret) {
3916 + pr_warn("MDIO access timeout\n");
3917 + return ret;
3918 + }
3919 +
3920 + if (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {
3921 + val = mtk_gmac_read(priv, GMAC_PIAC_REG);
3922 + return val & MDIO_RW_DATA_M;
3923 + }
3924 +
3925 + return 0;
3926 +}
3927 +
3928 +/* Direct MDIO clause 22 read via SoC */
3929 +int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
3930 +{
3931 + return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22);
3932 +}
3933 +
3934 +/* Direct MDIO clause 22 write via SoC */
3935 +int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data)
3936 +{
3937 + return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22);
3938 +}
3939 +
3940 +/* Direct MDIO clause 45 read via SoC */
3941 +int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
3942 +{
3943 + int ret;
3944 +
3945 + ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
3946 + if (ret)
3947 + return ret;
3948 +
3949 + return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45,
3950 + MDIO_ST_C45);
3951 +}
3952 +
3953 +/* Direct MDIO clause 45 write via SoC */
3954 +int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
3955 + u16 val)
3956 +{
3957 + int ret;
3958 +
3959 + ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
3960 + if (ret)
3961 + return ret;
3962 +
3963 + return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE,
3964 + MDIO_ST_C45);
3965 +}
3966 +
3967 +/* Indirect MDIO clause 45 read via MII registers */
3968 +int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
3969 +{
3970 + int ret;
3971 +
3972 + ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
3973 + (MMD_ADDR << MMD_CMD_S) |
3974 + ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
3975 + if (ret)
3976 + return ret;
3977 +
3978 + ret = mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
3979 + if (ret)
3980 + return ret;
3981 +
3982 + ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
3983 + (MMD_DATA << MMD_CMD_S) |
3984 + ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
3985 + if (ret)
3986 + return ret;
3987 +
3988 + return mtk_mii_read(priv, addr, MII_MMD_ADDR_DATA_REG);
3989 +}
3990 +
3991 +/* Indirect MDIO clause 45 write via MII registers */
3992 +int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
3993 + u16 val)
3994 +{
3995 + int ret;
3996 +
3997 + ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
3998 + (MMD_ADDR << MMD_CMD_S) |
3999 + ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
4000 + if (ret)
4001 + return ret;
4002 +
4003 + ret = mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
4004 + if (ret)
4005 + return ret;
4006 +
4007 + ret = mtk_mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
4008 + (MMD_DATA << MMD_CMD_S) |
4009 + ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
4010 + if (ret)
4011 + return ret;
4012 +
4013 + return mtk_mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val);
4014 +}
4015 +
4016 +static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
4017 +{
4018 + struct mtk_eth_priv *priv = bus->priv;
4019 +
4020 + if (devad < 0)
4021 + return mtk_mii_read(priv, addr, reg);
4022 +
4023 + return mtk_mmd_read(priv, addr, devad, reg);
4024 +}
4025 +
4026 +static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
4027 + u16 val)
4028 +{
4029 + struct mtk_eth_priv *priv = bus->priv;
4030 +
4031 + if (devad < 0)
4032 + return mtk_mii_write(priv, addr, reg, val);
4033 +
4034 + return mtk_mmd_write(priv, addr, devad, reg, val);
4035 +}
4036 +
4037 +static int mtk_mdio_register(struct udevice *dev)
4038 +{
4039 + struct mtk_eth_priv *priv = dev_get_priv(dev);
4040 + struct mii_dev *mdio_bus = mdio_alloc();
4041 + int ret;
4042 +
4043 + if (!mdio_bus)
4044 + return -ENOMEM;
4045 +
4046 + mdio_bus->read = mtk_mdio_read;
4047 + mdio_bus->write = mtk_mdio_write;
4048 + snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name);
4049 +
4050 + mdio_bus->priv = (void *)priv;
4051 +
4052 + ret = mdio_register(mdio_bus);
4053 +
4054 + if (ret)
4055 + return ret;
4056 +
4057 + priv->mdio_bus = mdio_bus;
4058 +
4059 + return 0;
4060 +}
4061 +
4062 +static int mtk_switch_init(struct mtk_eth_priv *priv)
4063 +{
4064 + struct mtk_eth_switch *swdrvs = ll_entry_start(struct mtk_eth_switch,
4065 + mtk_eth_switch);
4066 + const u32 n_swdrvs = ll_entry_count(struct mtk_eth_switch,
4067 + mtk_eth_switch);
4068 + struct mtk_eth_switch *tmp, *swdrv = NULL;
4069 + u32 reset_wait_time = 500;
4070 + size_t priv_size;
4071 + int ret;
4072 +
4073 + if (strcmp(priv->swname, "auto")) {
4074 + for (tmp = swdrvs; tmp < swdrvs + n_swdrvs; tmp++) {
4075 + if (!strcmp(tmp->name, priv->swname)) {
4076 + swdrv = tmp;
4077 + break;
4078 + }
4079 + }
4080 + }
4081 +
4082 + if (swdrv)
4083 + reset_wait_time = swdrv->reset_wait_time;
4084 +
4085 + /* Global reset switch */
4086 + if (priv->mcm) {
4087 + reset_assert(&priv->rst_mcm);
4088 + udelay(1000);
4089 + reset_deassert(&priv->rst_mcm);
4090 + mdelay(reset_wait_time);
4091 + } else if (dm_gpio_is_valid(&priv->rst_gpio)) {
4092 + dm_gpio_set_value(&priv->rst_gpio, 0);
4093 + udelay(1000);
4094 + dm_gpio_set_value(&priv->rst_gpio, 1);
4095 + mdelay(reset_wait_time);
4096 + }
4097 +
4098 + if (!swdrv) {
4099 + for (tmp = swdrvs; tmp < swdrvs + n_swdrvs; tmp++) {
4100 + if (!tmp->detect)
4101 + continue;
4102 +
4103 + ret = tmp->detect(priv);
4104 + if (!ret) {
4105 + swdrv = tmp;
4106 + break;
4107 + }
4108 + }
4109 +
4110 + if (!swdrv) {
4111 + printf("Error: unable to detect switch\n");
4112 + return -ENODEV;
4113 + }
4114 + } else {
4115 + if (swdrv->detect) {
4116 + ret = swdrv->detect(priv);
4117 + if (ret) {
4118 + printf("Error: switch probing failed\n");
4119 + return -ENODEV;
4120 + }
4121 + }
4122 + }
4123 +
4124 + printf("%s\n", swdrv->desc);
4125 +
4126 + priv_size = swdrv->priv_size;
4127 + if (priv_size < sizeof(struct mtk_eth_switch_priv))
4128 + priv_size = sizeof(struct mtk_eth_switch_priv);
4129 +
4130 + priv->swpriv = calloc(1, priv_size);
4131 + if (!priv->swpriv) {
4132 + printf("Error: no memory for switch data\n");
4133 + return -ENOMEM;
4134 + }
4135 +
4136 + priv->swpriv->eth = priv;
4137 + priv->swpriv->soc = priv->soc;
4138 + priv->swpriv->phy_interface = priv->phy_interface;
4139 + priv->swpriv->sw = swdrv;
4140 + priv->swpriv->ethsys_base = regmap_get_range(priv->ethsys_regmap, 0);
4141 +
4142 + ret = swdrv->setup(priv->swpriv);
4143 + if (ret) {
4144 + free(priv->swpriv);
4145 + priv->swpriv = NULL;
4146 + return ret;
4147 + }
4148 +
4149 + return 0;
4150 +}
4151 +
4152 +static void mtk_xphy_link_adjust(struct mtk_eth_priv *priv)
4153 +{
4154 + u16 lcl_adv = 0, rmt_adv = 0;
4155 + u8 flowctrl;
4156 + u32 mcr;
4157 +
4158 + mcr = mtk_gmac_read(priv, XGMAC_PORT_MCR(priv->gmac_id));
4159 + mcr &= ~(XGMAC_FORCE_TX_FC | XGMAC_FORCE_RX_FC);
4160 +
4161 + if (priv->phydev->duplex) {
4162 + if (priv->phydev->pause)
4163 + rmt_adv = LPA_PAUSE_CAP;
4164 + if (priv->phydev->asym_pause)
4165 + rmt_adv |= LPA_PAUSE_ASYM;
4166 +
4167 + if (priv->phydev->advertising & ADVERTISED_Pause)
4168 + lcl_adv |= ADVERTISE_PAUSE_CAP;
4169 + if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
4170 + lcl_adv |= ADVERTISE_PAUSE_ASYM;
4171 +
4172 + flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
4173 +
4174 + if (flowctrl & FLOW_CTRL_TX)
4175 + mcr |= XGMAC_FORCE_TX_FC;
4176 + if (flowctrl & FLOW_CTRL_RX)
4177 + mcr |= XGMAC_FORCE_RX_FC;
4178 +
4179 + debug("rx pause %s, tx pause %s\n",
4180 + flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
4181 + flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
4182 + }
4183 +
4184 + mcr &= ~(XGMAC_TRX_DISABLE);
4185 + mtk_gmac_write(priv, XGMAC_PORT_MCR(priv->gmac_id), mcr);
4186 +}
4187 +
4188 +static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
4189 +{
4190 + u16 lcl_adv = 0, rmt_adv = 0;
4191 + u8 flowctrl;
4192 + u32 mcr;
4193 +
4194 + mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
4195 + (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
4196 + MAC_MODE | FORCE_MODE |
4197 + MAC_TX_EN | MAC_RX_EN |
4198 + DEL_RXFIFO_CLR |
4199 + BKOFF_EN | BACKPR_EN;
4200 +
4201 + switch (priv->phydev->speed) {
4202 + case SPEED_10:
4203 + mcr |= (SPEED_10M << FORCE_SPD_S);
4204 + break;
4205 + case SPEED_100:
4206 + mcr |= (SPEED_100M << FORCE_SPD_S);
4207 + break;
4208 + case SPEED_1000:
4209 + case SPEED_2500:
4210 + mcr |= (SPEED_1000M << FORCE_SPD_S);
4211 + break;
4212 + };
4213 +
4214 + if (priv->phydev->link)
4215 + mcr |= FORCE_LINK;
4216 +
4217 + if (priv->phydev->duplex) {
4218 + mcr |= FORCE_DPX;
4219 +
4220 + if (priv->phydev->pause)
4221 + rmt_adv = LPA_PAUSE_CAP;
4222 + if (priv->phydev->asym_pause)
4223 + rmt_adv |= LPA_PAUSE_ASYM;
4224 +
4225 + if (priv->phydev->advertising & ADVERTISED_Pause)
4226 + lcl_adv |= ADVERTISE_PAUSE_CAP;
4227 + if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
4228 + lcl_adv |= ADVERTISE_PAUSE_ASYM;
4229 +
4230 + flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
4231 +
4232 + if (flowctrl & FLOW_CTRL_TX)
4233 + mcr |= FORCE_TX_FC;
4234 + if (flowctrl & FLOW_CTRL_RX)
4235 + mcr |= FORCE_RX_FC;
4236 +
4237 + debug("rx pause %s, tx pause %s\n",
4238 + flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
4239 + flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
4240 + }
4241 +
4242 + mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
4243 +}
4244 +
4245 +static int mtk_phy_start(struct mtk_eth_priv *priv)
4246 +{
4247 + struct phy_device *phydev = priv->phydev;
4248 + int ret;
4249 +
4250 + ret = phy_startup(phydev);
4251 +
4252 + if (ret) {
4253 + debug("Could not initialize PHY %s\n", phydev->dev->name);
4254 + return ret;
4255 + }
4256 +
4257 + if (!phydev->link) {
4258 + debug("%s: link down.\n", phydev->dev->name);
4259 + return 0;
4260 + }
4261 +
4262 + if (!priv->force_mode) {
4263 + if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
4264 + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
4265 + priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
4266 + mtk_xphy_link_adjust(priv);
4267 + else
4268 + mtk_phy_link_adjust(priv);
4269 + }
4270 +
4271 + debug("Speed: %d, %s duplex%s\n", phydev->speed,
4272 + (phydev->duplex) ? "full" : "half",
4273 + (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
4274 +
4275 + return 0;
4276 +}
4277 +
4278 +static int mtk_phy_probe(struct udevice *dev)
4279 +{
4280 + struct mtk_eth_priv *priv = dev_get_priv(dev);
4281 + struct phy_device *phydev;
4282 +
4283 + phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev,
4284 + priv->phy_interface);
4285 + if (!phydev)
4286 + return -ENODEV;
4287 +
4288 + phydev->supported &= PHY_GBIT_FEATURES;
4289 + phydev->advertising = phydev->supported;
4290 +
4291 + priv->phydev = phydev;
4292 + phy_config(phydev);
4293 +
4294 + return 0;
4295 +}
4296 +
4297 +static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
4298 +{
4299 + /* Set SGMII GEN1 speed(1G) */
4300 + clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK);
4301 +
4302 + /* Enable SGMII AN */
4303 + setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
4304 + SGMII_AN_ENABLE);
4305 +
4306 + /* SGMII AN mode setting */
4307 + writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
4308 +
4309 + /* SGMII PN SWAP setting */
4310 + if (priv->pn_swap) {
4311 + setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
4312 + SGMII_PN_SWAP_TX_RX);
4313 + }
4314 +
4315 + /* Release PHYA power down state */
4316 + clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
4317 + SGMII_PHYA_PWD, 0);
4318 +}
4319 +
4320 +static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
4321 +{
4322 + /* Set SGMII GEN2 speed(2.5G) */
4323 + clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
4324 + SGMSYS_SPEED_MASK,
4325 + FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500));
4326 +
4327 + /* Disable SGMII AN */
4328 + clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
4329 + SGMII_AN_ENABLE, 0);
4330 +
4331 + /* SGMII force mode setting */
4332 + writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
4333 +
4334 + /* SGMII PN SWAP setting */
4335 + if (priv->pn_swap) {
4336 + setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
4337 + SGMII_PN_SWAP_TX_RX);
4338 + }
4339 +
4340 + /* Release PHYA power down state */
4341 + clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
4342 + SGMII_PHYA_PWD, 0);
4343 +}
4344 +
4345 +static void mtk_xfi_pll_enable(struct mtk_eth_priv *priv)
4346 +{
4347 + u32 val = 0;
4348 +
4349 + /* Add software workaround for USXGMII PLL TCL issue */
4350 + regmap_write(priv->xfi_pll_regmap, XFI_PLL_ANA_GLB8,
4351 + RG_XFI_PLL_ANA_SWWA);
4352 +
4353 + regmap_read(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, &val);
4354 + val |= RG_XFI_PLL_EN;
4355 + regmap_write(priv->xfi_pll_regmap, XFI_PLL_DIG_GLB8, val);
4356 +}
4357 +
4358 +static void mtk_usxgmii_reset(struct mtk_eth_priv *priv)
4359 +{
4360 + switch (priv->gmac_id) {
4361 + case 1:
4362 + regmap_write(priv->toprgu_regmap, 0xFC, 0x0000A004);
4363 + regmap_write(priv->toprgu_regmap, 0x18, 0x88F0A004);
4364 + regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
4365 + regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
4366 + regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
4367 + break;
4368 + case 2:
4369 + regmap_write(priv->toprgu_regmap, 0xFC, 0x00005002);
4370 + regmap_write(priv->toprgu_regmap, 0x18, 0x88F05002);
4371 + regmap_write(priv->toprgu_regmap, 0xFC, 0x00000000);
4372 + regmap_write(priv->toprgu_regmap, 0x18, 0x88F00000);
4373 + regmap_write(priv->toprgu_regmap, 0x18, 0x00F00000);
4374 + break;
4375 + }
4376 +
4377 + mdelay(10);
4378 +}
4379 +
4380 +static void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth_priv *priv)
4381 +{
4382 + regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6D);
4383 + regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
4384 + regmap_write(priv->usxgmii_regmap, 0x80C, 0x30000000);
4385 + ndelay(1020);
4386 + regmap_write(priv->usxgmii_regmap, 0x80C, 0x10000000);
4387 + ndelay(1020);
4388 + regmap_write(priv->usxgmii_regmap, 0x80C, 0x00000000);
4389 +
4390 + regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
4391 + regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
4392 + regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
4393 + regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
4394 + regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
4395 + regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
4396 + regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
4397 + regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
4398 + regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
4399 + regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
4400 + regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
4401 + regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
4402 + regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
4403 + regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
4404 + regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
4405 + regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
4406 + regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
4407 + regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
4408 + regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
4409 + regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
4410 + regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
4411 + regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
4412 + regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
4413 + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
4414 + ndelay(1020);
4415 + regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
4416 + regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
4417 + regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
4418 + regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
4419 + regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
4420 + regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
4421 + regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
4422 + regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x40704000);
4423 + regmap_write(priv->xfi_pextp_regmap, 0x3050, 0xA8000000);
4424 + regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x000000AA);
4425 + regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
4426 + regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
4427 + regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
4428 + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
4429 + udelay(150);
4430 + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
4431 + ndelay(1020);
4432 + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
4433 + udelay(15);
4434 + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
4435 + ndelay(1020);
4436 + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
4437 + udelay(100);
4438 + regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
4439 + regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
4440 + regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
4441 + udelay(400);
4442 +}
4443 +
4444 +static void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth_priv *priv)
4445 +{
4446 + regmap_write(priv->usxgmii_regmap, 0x810, 0x000FFE6C);
4447 + regmap_write(priv->usxgmii_regmap, 0x818, 0x07B1EC7B);
4448 + regmap_write(priv->usxgmii_regmap, 0x80C, 0xB0000000);
4449 + ndelay(1020);
4450 + regmap_write(priv->usxgmii_regmap, 0x80C, 0x90000000);
4451 + ndelay(1020);
4452 +
4453 + regmap_write(priv->xfi_pextp_regmap, 0x9024, 0x00C9071C);
4454 + regmap_write(priv->xfi_pextp_regmap, 0x2020, 0xAA8585AA);
4455 + regmap_write(priv->xfi_pextp_regmap, 0x2030, 0x0C020707);
4456 + regmap_write(priv->xfi_pextp_regmap, 0x2034, 0x0E050F0F);
4457 + regmap_write(priv->xfi_pextp_regmap, 0x2040, 0x00140032);
4458 + regmap_write(priv->xfi_pextp_regmap, 0x50F0, 0x00C014AA);
4459 + regmap_write(priv->xfi_pextp_regmap, 0x50E0, 0x3777C12B);
4460 + regmap_write(priv->xfi_pextp_regmap, 0x506C, 0x005F9CFF);
4461 + regmap_write(priv->xfi_pextp_regmap, 0x5070, 0x9D9DFAFA);
4462 + regmap_write(priv->xfi_pextp_regmap, 0x5074, 0x27273F3F);
4463 + regmap_write(priv->xfi_pextp_regmap, 0x5078, 0xA7883C68);
4464 + regmap_write(priv->xfi_pextp_regmap, 0x507C, 0x11661166);
4465 + regmap_write(priv->xfi_pextp_regmap, 0x5080, 0x0E000AAF);
4466 + regmap_write(priv->xfi_pextp_regmap, 0x5084, 0x08080D0D);
4467 + regmap_write(priv->xfi_pextp_regmap, 0x5088, 0x02030909);
4468 + regmap_write(priv->xfi_pextp_regmap, 0x50E4, 0x0C0C0000);
4469 + regmap_write(priv->xfi_pextp_regmap, 0x50E8, 0x04040000);
4470 + regmap_write(priv->xfi_pextp_regmap, 0x50EC, 0x0F0F0C06);
4471 + regmap_write(priv->xfi_pextp_regmap, 0x50A8, 0x506E8C8C);
4472 + regmap_write(priv->xfi_pextp_regmap, 0x6004, 0x18190000);
4473 + regmap_write(priv->xfi_pextp_regmap, 0x00F8, 0x01423342);
4474 + regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F20);
4475 + regmap_write(priv->xfi_pextp_regmap, 0x0030, 0x00050C00);
4476 + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x02002800);
4477 + ndelay(1020);
4478 + regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000020);
4479 + regmap_write(priv->xfi_pextp_regmap, 0x3028, 0x00008A01);
4480 + regmap_write(priv->xfi_pextp_regmap, 0x302C, 0x0000A884);
4481 + regmap_write(priv->xfi_pextp_regmap, 0x3024, 0x00083002);
4482 + regmap_write(priv->xfi_pextp_regmap, 0x3010, 0x00022220);
4483 + regmap_write(priv->xfi_pextp_regmap, 0x5064, 0x0F020A01);
4484 + regmap_write(priv->xfi_pextp_regmap, 0x50B4, 0x06100600);
4485 + regmap_write(priv->xfi_pextp_regmap, 0x3048, 0x47684100);
4486 + regmap_write(priv->xfi_pextp_regmap, 0x3050, 0x00000000);
4487 + regmap_write(priv->xfi_pextp_regmap, 0x3054, 0x00000000);
4488 + regmap_write(priv->xfi_pextp_regmap, 0x306C, 0x00000F00);
4489 + if (priv->gmac_id == 2)
4490 + regmap_write(priv->xfi_pextp_regmap, 0xA008, 0x0007B400);
4491 + regmap_write(priv->xfi_pextp_regmap, 0xA060, 0x00040000);
4492 + regmap_write(priv->xfi_pextp_regmap, 0x90D0, 0x00000001);
4493 + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200E800);
4494 + udelay(150);
4495 + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C111);
4496 + ndelay(1020);
4497 + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0200C101);
4498 + udelay(15);
4499 + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C111);
4500 + ndelay(1020);
4501 + regmap_write(priv->xfi_pextp_regmap, 0x0070, 0x0202C101);
4502 + udelay(100);
4503 + regmap_write(priv->xfi_pextp_regmap, 0x30B0, 0x00000030);
4504 + regmap_write(priv->xfi_pextp_regmap, 0x00F4, 0x80201F00);
4505 + regmap_write(priv->xfi_pextp_regmap, 0x3040, 0x30000000);
4506 + udelay(400);
4507 +}
4508 +
4509 +static void mtk_usxgmii_an_init(struct mtk_eth_priv *priv)
4510 +{
4511 + mtk_xfi_pll_enable(priv);
4512 + mtk_usxgmii_reset(priv);
4513 + mtk_usxgmii_setup_phya_an_10000(priv);
4514 +}
4515 +
4516 +static void mtk_10gbaser_init(struct mtk_eth_priv *priv)
4517 +{
4518 + mtk_xfi_pll_enable(priv);
4519 + mtk_usxgmii_reset(priv);
4520 + mtk_usxgmii_setup_phya_force_10000(priv);
4521 +}
4522 +
4523 +static int mtk_mac_init(struct mtk_eth_priv *priv)
4524 +{
4525 + int i, sgmii_sel_mask = 0, ge_mode = 0;
4526 + u32 mcr;
4527 +
4528 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7629_GMAC2)) {
4529 + mtk_infra_rmw(priv, MT7629_INFRA_MISC2_REG,
4530 + INFRA_MISC2_BONDING_OPTION, priv->gmac_id);
4531 + }
4532 +
4533 + switch (priv->phy_interface) {
4534 + case PHY_INTERFACE_MODE_RGMII_RXID:
4535 + case PHY_INTERFACE_MODE_RGMII:
4536 + ge_mode = GE_MODE_RGMII;
4537 + break;
4538 + case PHY_INTERFACE_MODE_SGMII:
4539 + case PHY_INTERFACE_MODE_2500BASEX:
4540 + if (!IS_ENABLED(CONFIG_MTK_ETH_SGMII)) {
4541 + printf("Error: SGMII is not supported on this platform\n");
4542 + return -ENOTSUPP;
4543 + }
4544 +
4545 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) {
4546 + mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK,
4547 + SGMII_QPHY_SEL);
4548 + }
4549 +
4550 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_ETH_PATH_MT7622_SGMII))
4551 + sgmii_sel_mask = SYSCFG1_SGMII_SEL_M;
4552 +
4553 + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, sgmii_sel_mask,
4554 + SYSCFG1_SGMII_SEL(priv->gmac_id));
4555 +
4556 + if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
4557 + mtk_sgmii_an_init(priv);
4558 + else
4559 + mtk_sgmii_force_init(priv);
4560 +
4561 + ge_mode = GE_MODE_RGMII;
4562 + break;
4563 + case PHY_INTERFACE_MODE_MII:
4564 + case PHY_INTERFACE_MODE_GMII:
4565 + ge_mode = GE_MODE_MII;
4566 + break;
4567 + case PHY_INTERFACE_MODE_RMII:
4568 + ge_mode = GE_MODE_RMII;
4569 + break;
4570 + default:
4571 + break;
4572 + }
4573 +
4574 + /* set the gmac to the right mode */
4575 + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG,
4576 + SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
4577 + ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id));
4578 +
4579 + if (priv->force_mode) {
4580 + mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
4581 + (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
4582 + MAC_MODE | FORCE_MODE |
4583 + MAC_TX_EN | MAC_RX_EN |
4584 + BKOFF_EN | BACKPR_EN |
4585 + FORCE_LINK;
4586 +
4587 + switch (priv->speed) {
4588 + case SPEED_10:
4589 + mcr |= SPEED_10M << FORCE_SPD_S;
4590 + break;
4591 + case SPEED_100:
4592 + mcr |= SPEED_100M << FORCE_SPD_S;
4593 + break;
4594 + case SPEED_1000:
4595 + case SPEED_2500:
4596 + mcr |= SPEED_1000M << FORCE_SPD_S;
4597 + break;
4598 + }
4599 +
4600 + if (priv->duplex)
4601 + mcr |= FORCE_DPX;
4602 +
4603 + mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
4604 + }
4605 +
4606 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC1_TRGMII) &&
4607 + !MTK_HAS_CAPS(priv->soc->caps, MTK_TRGMII_MT7621_CLK)) {
4608 + /* Lower Tx Driving for TRGMII path */
4609 + for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
4610 + mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i),
4611 + (8 << TD_DM_DRVP_S) |
4612 + (8 << TD_DM_DRVN_S));
4613 +
4614 + mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0,
4615 + RX_RST | RXC_DQSISEL);
4616 + mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0);
4617 + }
4618 +
4619 + return 0;
4620 +}
4621 +
4622 +static int mtk_xmac_init(struct mtk_eth_priv *priv)
4623 +{
4624 + u32 force_link = 0;
4625 +
4626 + if (!IS_ENABLED(CONFIG_MTK_ETH_XGMII)) {
4627 + printf("Error: 10Gb interface is not supported on this platform\n");
4628 + return -ENOTSUPP;
4629 + }
4630 +
4631 + switch (priv->phy_interface) {
4632 + case PHY_INTERFACE_MODE_USXGMII:
4633 + mtk_usxgmii_an_init(priv);
4634 + break;
4635 + case PHY_INTERFACE_MODE_10GBASER:
4636 + mtk_10gbaser_init(priv);
4637 + break;
4638 + default:
4639 + break;
4640 + }
4641 +
4642 + /* Set GMAC to the correct mode */
4643 + mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG,
4644 + SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
4645 + 0);
4646 +
4647 + if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
4648 + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) &&
4649 + priv->gmac_id == 1) {
4650 + mtk_infra_rmw(priv, TOPMISC_NETSYS_PCS_MUX,
4651 + NETSYS_PCS_MUX_MASK, MUX_G2_USXGMII_SEL);
4652 + }
4653 +
4654 + if (priv->phy_interface == PHY_INTERFACE_MODE_XGMII ||
4655 + priv->gmac_id == 2)
4656 + force_link = XGMAC_FORCE_LINK(priv->gmac_id);
4657 +
4658 + mtk_gmac_rmw(priv, XGMAC_STS(priv->gmac_id),
4659 + XGMAC_FORCE_LINK(priv->gmac_id), force_link);
4660 +
4661 + /* Force GMAC link down */
4662 + mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), FORCE_MODE);
4663 +
4664 + return 0;
4665 +}
4666 +
4667 +static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
4668 +{
4669 + char *pkt_base = priv->pkt_pool;
4670 + struct mtk_tx_dma_v2 *txd;
4671 + struct mtk_rx_dma_v2 *rxd;
4672 + int i;
4673 +
4674 + mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0);
4675 + udelay(500);
4676 +
4677 + memset(priv->tx_ring_noc, 0, NUM_TX_DESC * priv->soc->txd_size);
4678 + memset(priv->rx_ring_noc, 0, NUM_RX_DESC * priv->soc->rxd_size);
4679 + memset(priv->pkt_pool, 0xff, TOTAL_PKT_BUF_SIZE);
4680 +
4681 + flush_dcache_range((ulong)pkt_base,
4682 + (ulong)(pkt_base + TOTAL_PKT_BUF_SIZE));
4683 +
4684 + priv->rx_dma_owner_idx0 = 0;
4685 + priv->tx_cpu_owner_idx0 = 0;
4686 +
4687 + for (i = 0; i < NUM_TX_DESC; i++) {
4688 + txd = priv->tx_ring_noc + i * priv->soc->txd_size;
4689 +
4690 + txd->txd1 = virt_to_phys(pkt_base);
4691 + txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0;
4692 +
4693 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
4694 + txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ?
4695 + 15 : priv->gmac_id + 1);
4696 + else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
4697 + txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1);
4698 + else
4699 + txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1);
4700 +
4701 + pkt_base += PKTSIZE_ALIGN;
4702 + }
4703 +
4704 + for (i = 0; i < NUM_RX_DESC; i++) {
4705 + rxd = priv->rx_ring_noc + i * priv->soc->rxd_size;
4706 +
4707 + rxd->rxd1 = virt_to_phys(pkt_base);
4708 +
4709 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
4710 + MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
4711 + rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
4712 + else
4713 + rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
4714 +
4715 + pkt_base += PKTSIZE_ALIGN;
4716 + }
4717 +
4718 + mtk_pdma_write(priv, TX_BASE_PTR_REG(0),
4719 + virt_to_phys(priv->tx_ring_noc));
4720 + mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC);
4721 + mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
4722 +
4723 + mtk_pdma_write(priv, RX_BASE_PTR_REG(0),
4724 + virt_to_phys(priv->rx_ring_noc));
4725 + mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC);
4726 + mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1);
4727 +
4728 + mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0);
4729 +}
4730 +
4731 +static void mtk_eth_mdc_init(struct mtk_eth_priv *priv)
4732 +{
4733 + u32 divider;
4734 +
4735 + if (priv->mdc == 0)
4736 + return;
4737 +
4738 + divider = min_t(u32, DIV_ROUND_UP(MDC_MAX_FREQ, priv->mdc), MDC_MAX_DIVIDER);
4739 +
4740 + /* Configure MDC turbo mode */
4741 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
4742 + mtk_gmac_rmw(priv, GMAC_MAC_MISC_REG, 0, MISC_MDC_TURBO);
4743 + else
4744 + mtk_gmac_rmw(priv, GMAC_PPSC_REG, 0, MISC_MDC_TURBO);
4745 +
4746 + /* Configure MDC divider */
4747 + mtk_gmac_rmw(priv, GMAC_PPSC_REG, PHY_MDC_CFG,
4748 + FIELD_PREP(PHY_MDC_CFG, divider));
4749 +}
4750 +
4751 +static int mtk_eth_start(struct udevice *dev)
4752 +{
4753 + struct mtk_eth_priv *priv = dev_get_priv(dev);
4754 + int i, ret;
4755 +
4756 + /* Reset FE */
4757 + reset_assert(&priv->rst_fe);
4758 + udelay(1000);
4759 + reset_deassert(&priv->rst_fe);
4760 + mdelay(10);
4761 +
4762 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
4763 + MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
4764 + setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2);
4765 +
4766 + /* Packets forward to PDMA */
4767 + mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
4768 +
4769 + for (i = 0; i < priv->soc->gdma_count; i++) {
4770 + if (i == priv->gmac_id)
4771 + continue;
4772 +
4773 + mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
4774 + }
4775 +
4776 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
4777 + if (priv->swpriv && !strcmp(priv->swpriv->sw->name, "mt7988") &&
4778 + priv->gmac_id == 0) {
4779 + mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG,
4780 + GDMA_BRIDGE_TO_CPU);
4781 +
4782 + mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
4783 + GDMA_CPU_BRIDGE_EN);
4784 + } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
4785 + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
4786 + priv->phy_interface == PHY_INTERFACE_MODE_XGMII) &&
4787 + priv->gmac_id != 0) {
4788 + mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
4789 + GDMA_CPU_BRIDGE_EN);
4790 + }
4791 + }
4792 +
4793 + udelay(500);
4794 +
4795 + mtk_eth_fifo_init(priv);
4796 +
4797 + if (priv->swpriv) {
4798 + /* Enable communication with switch */
4799 + if (priv->swpriv->sw->mac_control)
4800 + priv->swpriv->sw->mac_control(priv->swpriv, true);
4801 + } else {
4802 + /* Start PHY */
4803 + ret = mtk_phy_start(priv);
4804 + if (ret)
4805 + return ret;
4806 + }
4807 +
4808 + mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0,
4809 + TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
4810 + udelay(500);
4811 +
4812 + return 0;
4813 +}
4814 +
4815 +static void mtk_eth_stop(struct udevice *dev)
4816 +{
4817 + struct mtk_eth_priv *priv = dev_get_priv(dev);
4818 +
4819 + if (priv->swpriv) {
4820 + if (priv->swpriv->sw->mac_control)
4821 + priv->swpriv->sw->mac_control(priv->swpriv, false);
4822 + }
4823 +
4824 + mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
4825 + TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
4826 + udelay(500);
4827 +
4828 + wait_for_bit_le32(priv->fe_base + priv->soc->pdma_base + PDMA_GLO_CFG_REG,
4829 + RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0);
4830 +}
4831 +
4832 +static int mtk_eth_write_hwaddr(struct udevice *dev)
4833 +{
4834 + struct eth_pdata *pdata = dev_get_plat(dev);
4835 + struct mtk_eth_priv *priv = dev_get_priv(dev);
4836 + unsigned char *mac = pdata->enetaddr;
4837 + u32 macaddr_lsb, macaddr_msb;
4838 +
4839 + macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1];
4840 + macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) |
4841 + ((u32)mac[4] << 8) | (u32)mac[5];
4842 +
4843 + mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb);
4844 + mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb);
4845 +
4846 + return 0;
4847 +}
4848 +
4849 +static int mtk_eth_send(struct udevice *dev, void *packet, int length)
4850 +{
4851 + struct mtk_eth_priv *priv = dev_get_priv(dev);
4852 + u32 idx = priv->tx_cpu_owner_idx0;
4853 + struct mtk_tx_dma_v2 *txd;
4854 + void *pkt_base;
4855 +
4856 + txd = priv->tx_ring_noc + idx * priv->soc->txd_size;
4857 +
4858 + if (!(txd->txd2 & PDMA_TXD2_DDONE)) {
4859 + debug("mtk-eth: TX DMA descriptor ring is full\n");
4860 + return -EPERM;
4861 + }
4862 +
4863 + pkt_base = (void *)phys_to_virt(txd->txd1);
4864 + memcpy(pkt_base, packet, length);
4865 + flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
4866 + roundup(length, ARCH_DMA_MINALIGN));
4867 +
4868 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
4869 + MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
4870 + txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length);
4871 + else
4872 + txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length);
4873 +
4874 + priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC;
4875 + mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
4876 +
4877 + return 0;
4878 +}
4879 +
4880 +static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp)
4881 +{
4882 + struct mtk_eth_priv *priv = dev_get_priv(dev);
4883 + u32 idx = priv->rx_dma_owner_idx0;
4884 + struct mtk_rx_dma_v2 *rxd;
4885 + uchar *pkt_base;
4886 + u32 length;
4887 +
4888 + rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
4889 +
4890 + if (!(rxd->rxd2 & PDMA_RXD2_DDONE)) {
4891 + debug("mtk-eth: RX DMA descriptor ring is empty\n");
4892 + return -EAGAIN;
4893 + }
4894 +
4895 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
4896 + MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
4897 + length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2);
4898 + else
4899 + length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2);
4900 +
4901 + pkt_base = (void *)phys_to_virt(rxd->rxd1);
4902 + invalidate_dcache_range((ulong)pkt_base, (ulong)pkt_base +
4903 + roundup(length, ARCH_DMA_MINALIGN));
4904 +
4905 + if (packetp)
4906 + *packetp = pkt_base;
4907 +
4908 + return length;
4909 +}
4910 +
4911 +static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
4912 +{
4913 + struct mtk_eth_priv *priv = dev_get_priv(dev);
4914 + u32 idx = priv->rx_dma_owner_idx0;
4915 + struct mtk_rx_dma_v2 *rxd;
4916 +
4917 + rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
4918 +
4919 + invalidate_dcache_range((ulong)rxd->rxd1,
4920 + (ulong)rxd->rxd1 + PKTSIZE_ALIGN);
4921 +
4922 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
4923 + MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
4924 + rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
4925 + else
4926 + rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
4927 +
4928 + mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx);
4929 + priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC;
4930 +
4931 + return 0;
4932 +}
4933 +
4934 +static int mtk_eth_probe(struct udevice *dev)
4935 +{
4936 + struct eth_pdata *pdata = dev_get_plat(dev);
4937 + struct mtk_eth_priv *priv = dev_get_priv(dev);
4938 + ulong iobase = pdata->iobase;
4939 + int ret;
4940 +
4941 + /* Frame Engine Register Base */
4942 + priv->fe_base = (void *)iobase;
4943 +
4944 + /* GMAC Register Base */
4945 + priv->gmac_base = (void *)(iobase + GMAC_BASE);
4946 +
4947 + /* MDIO register */
4948 + ret = mtk_mdio_register(dev);
4949 + if (ret)
4950 + return ret;
4951 +
4952 + /* Prepare for tx/rx rings */
4953 + priv->tx_ring_noc = (void *)
4954 + noncached_alloc(priv->soc->txd_size * NUM_TX_DESC,
4955 + ARCH_DMA_MINALIGN);
4956 + priv->rx_ring_noc = (void *)
4957 + noncached_alloc(priv->soc->rxd_size * NUM_RX_DESC,
4958 + ARCH_DMA_MINALIGN);
4959 +
4960 + /* Set MDC divider */
4961 + mtk_eth_mdc_init(priv);
4962 +
4963 + /* Set MAC mode */
4964 + if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
4965 + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER ||
4966 + priv->phy_interface == PHY_INTERFACE_MODE_XGMII)
4967 + ret = mtk_xmac_init(priv);
4968 + else
4969 + ret = mtk_mac_init(priv);
4970 +
4971 + if (ret)
4972 + return ret;
4973 +
4974 + /* Probe phy if switch is not specified */
4975 + if (!priv->swname)
4976 + return mtk_phy_probe(dev);
4977 +
4978 + /* Initialize switch */
4979 + return mtk_switch_init(priv);
4980 +}
4981 +
4982 +static int mtk_eth_remove(struct udevice *dev)
4983 +{
4984 + struct mtk_eth_priv *priv = dev_get_priv(dev);
4985 +
4986 + /* MDIO unregister */
4987 + mdio_unregister(priv->mdio_bus);
4988 + mdio_free(priv->mdio_bus);
4989 +
4990 + /* Stop possibly started DMA */
4991 + mtk_eth_stop(dev);
4992 +
4993 + if (priv->swpriv) {
4994 + if (priv->swpriv->sw->cleanup)
4995 + priv->swpriv->sw->cleanup(priv->swpriv);
4996 + free(priv->swpriv);
4997 + }
4998 +
4999 + return 0;
5000 +}
5001 +
5002 +static int mtk_eth_of_to_plat(struct udevice *dev)
5003 +{
5004 + struct eth_pdata *pdata = dev_get_plat(dev);
5005 + struct mtk_eth_priv *priv = dev_get_priv(dev);
5006 + struct ofnode_phandle_args args;
5007 + struct regmap *regmap;
5008 + ofnode subnode;
5009 + int ret;
5010 +
5011 + priv->soc = (const struct mtk_soc_data *)dev_get_driver_data(dev);
5012 + if (!priv->soc) {
5013 + dev_err(dev, "missing soc compatible data\n");
5014 + return -EINVAL;
5015 + }
5016 +
5017 + pdata->iobase = (phys_addr_t)dev_remap_addr(dev);
5018 +
5019 + /* get corresponding ethsys phandle */
5020 + ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0,
5021 + &args);
5022 + if (ret)
5023 + return ret;
5024 +
5025 + priv->ethsys_regmap = syscon_node_to_regmap(args.node);
5026 + if (IS_ERR(priv->ethsys_regmap))
5027 + return PTR_ERR(priv->ethsys_regmap);
5028 +
5029 + if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) {
5030 + /* get corresponding infracfg phandle */
5031 + ret = dev_read_phandle_with_args(dev, "mediatek,infracfg",
5032 + NULL, 0, 0, &args);
5033 +
5034 + if (ret)
5035 + return ret;
5036 +
5037 + priv->infra_regmap = syscon_node_to_regmap(args.node);
5038 + if (IS_ERR(priv->infra_regmap))
5039 + return PTR_ERR(priv->infra_regmap);
5040 + }
5041 +
5042 + /* Reset controllers */
5043 + ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
5044 + if (ret) {
5045 + printf("error: Unable to get reset ctrl for frame engine\n");
5046 + return ret;
5047 + }
5048 +
5049 + priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0);
5050 +
5051 + priv->mdc = 0;
5052 + subnode = ofnode_find_subnode(dev_ofnode(dev), "mdio");
5053 + if (ofnode_valid(subnode)) {
5054 + priv->mdc = ofnode_read_u32_default(subnode, "clock-frequency", 2500000);
5055 + if (priv->mdc > MDC_MAX_FREQ ||
5056 + priv->mdc < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
5057 + printf("error: MDIO clock frequency out of range\n");
5058 + return -EINVAL;
5059 + }
5060 + }
5061 +
5062 + /* Interface mode is required */
5063 + pdata->phy_interface = dev_read_phy_mode(dev);
5064 + priv->phy_interface = pdata->phy_interface;
5065 + if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
5066 + printf("error: phy-mode is not set\n");
5067 + return -EINVAL;
5068 + }
5069 +
5070 + /* Force mode or autoneg */
5071 + subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link");
5072 + if (ofnode_valid(subnode)) {
5073 + priv->force_mode = 1;
5074 + priv->speed = ofnode_read_u32_default(subnode, "speed", 0);
5075 + priv->duplex = ofnode_read_bool(subnode, "full-duplex");
5076 +
5077 + if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
5078 + priv->speed != SPEED_1000 && priv->speed != SPEED_2500 &&
5079 + priv->speed != SPEED_10000) {
5080 + printf("error: no valid speed set in fixed-link\n");
5081 + return -EINVAL;
5082 + }
5083 + }
5084 +
5085 + if ((priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
5086 + priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) &&
5087 + IS_ENABLED(CONFIG_MTK_ETH_SGMII)) {
5088 + /* get corresponding sgmii phandle */
5089 + ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
5090 + NULL, 0, 0, &args);
5091 + if (ret)
5092 + return ret;
5093 +
5094 + regmap = syscon_node_to_regmap(args.node);
5095 +
5096 + if (IS_ERR(regmap))
5097 + return PTR_ERR(regmap);
5098 +
5099 + priv->sgmii_base = regmap_get_range(regmap, 0);
5100 +
5101 + if (!priv->sgmii_base) {
5102 + dev_err(dev, "Unable to find sgmii\n");
5103 + return -ENODEV;
5104 + }
5105 +
5106 + /* Upstream linux use mediatek,pnswap instead of pn_swap */
5107 + priv->pn_swap = ofnode_read_bool(args.node, "pn_swap") ||
5108 + ofnode_read_bool(args.node, "mediatek,pnswap");
5109 + } else if ((priv->phy_interface == PHY_INTERFACE_MODE_USXGMII ||
5110 + priv->phy_interface == PHY_INTERFACE_MODE_10GBASER) &&
5111 + IS_ENABLED(CONFIG_MTK_ETH_XGMII)) {
5112 + /* get corresponding usxgmii phandle */
5113 + ret = dev_read_phandle_with_args(dev, "mediatek,usxgmiisys",
5114 + NULL, 0, 0, &args);
5115 + if (ret)
5116 + return ret;
5117 +
5118 + priv->usxgmii_regmap = syscon_node_to_regmap(args.node);
5119 + if (IS_ERR(priv->usxgmii_regmap))
5120 + return PTR_ERR(priv->usxgmii_regmap);
5121 +
5122 + /* get corresponding xfi_pextp phandle */
5123 + ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pextp",
5124 + NULL, 0, 0, &args);
5125 + if (ret)
5126 + return ret;
5127 +
5128 + priv->xfi_pextp_regmap = syscon_node_to_regmap(args.node);
5129 + if (IS_ERR(priv->xfi_pextp_regmap))
5130 + return PTR_ERR(priv->xfi_pextp_regmap);
5131 +
5132 + /* get corresponding xfi_pll phandle */
5133 + ret = dev_read_phandle_with_args(dev, "mediatek,xfi_pll",
5134 + NULL, 0, 0, &args);
5135 + if (ret)
5136 + return ret;
5137 +
5138 + priv->xfi_pll_regmap = syscon_node_to_regmap(args.node);
5139 + if (IS_ERR(priv->xfi_pll_regmap))
5140 + return PTR_ERR(priv->xfi_pll_regmap);
5141 +
5142 + /* get corresponding toprgu phandle */
5143 + ret = dev_read_phandle_with_args(dev, "mediatek,toprgu",
5144 + NULL, 0, 0, &args);
5145 + if (ret)
5146 + return ret;
5147 +
5148 + priv->toprgu_regmap = syscon_node_to_regmap(args.node);
5149 + if (IS_ERR(priv->toprgu_regmap))
5150 + return PTR_ERR(priv->toprgu_regmap);
5151 + }
5152 +
5153 + priv->swname = dev_read_string(dev, "mediatek,switch");
5154 + if (priv->swname) {
5155 + priv->mcm = dev_read_bool(dev, "mediatek,mcm");
5156 + if (priv->mcm) {
5157 + ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm);
5158 + if (ret) {
5159 + printf("error: no reset ctrl for mcm\n");
5160 + return ret;
5161 + }
5162 + } else {
5163 + gpio_request_by_name(dev, "reset-gpios", 0,
5164 + &priv->rst_gpio, GPIOD_IS_OUT);
5165 + }
5166 + } else {
5167 + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0,
5168 + 0, &args);
5169 + if (ret) {
5170 + printf("error: phy-handle is not specified\n");
5171 + return ret;
5172 + }
5173 +
5174 + priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1);
5175 + if (priv->phy_addr < 0) {
5176 + printf("error: phy address is not specified\n");
5177 + return ret;
5178 + }
5179 + }
5180 +
5181 + return 0;
5182 +}
5183 +
5184 +static const struct mtk_soc_data mt7988_data = {
5185 + .caps = MT7988_CAPS,
5186 + .ana_rgc3 = 0x128,
5187 + .gdma_count = 3,
5188 + .pdma_base = PDMA_V3_BASE,
5189 + .txd_size = sizeof(struct mtk_tx_dma_v2),
5190 + .rxd_size = sizeof(struct mtk_rx_dma_v2),
5191 +};
5192 +
5193 +static const struct mtk_soc_data mt7986_data = {
5194 + .caps = MT7986_CAPS,
5195 + .ana_rgc3 = 0x128,
5196 + .gdma_count = 2,
5197 + .pdma_base = PDMA_V2_BASE,
5198 + .txd_size = sizeof(struct mtk_tx_dma_v2),
5199 + .rxd_size = sizeof(struct mtk_rx_dma_v2),
5200 +};
5201 +
5202 +static const struct mtk_soc_data mt7981_data = {
5203 + .caps = MT7981_CAPS,
5204 + .ana_rgc3 = 0x128,
5205 + .gdma_count = 2,
5206 + .pdma_base = PDMA_V2_BASE,
5207 + .txd_size = sizeof(struct mtk_tx_dma_v2),
5208 + .rxd_size = sizeof(struct mtk_rx_dma_v2),
5209 +};
5210 +
5211 +static const struct mtk_soc_data mt7629_data = {
5212 + .caps = MT7629_CAPS,
5213 + .ana_rgc3 = 0x128,
5214 + .gdma_count = 2,
5215 + .pdma_base = PDMA_V1_BASE,
5216 + .txd_size = sizeof(struct mtk_tx_dma),
5217 + .rxd_size = sizeof(struct mtk_rx_dma),
5218 +};
5219 +
5220 +static const struct mtk_soc_data mt7623_data = {
5221 + .caps = MT7623_CAPS,
5222 + .gdma_count = 2,
5223 + .pdma_base = PDMA_V1_BASE,
5224 + .txd_size = sizeof(struct mtk_tx_dma),
5225 + .rxd_size = sizeof(struct mtk_rx_dma),
5226 +};
5227 +
5228 +static const struct mtk_soc_data mt7622_data = {
5229 + .caps = MT7622_CAPS,
5230 + .ana_rgc3 = 0x2028,
5231 + .gdma_count = 2,
5232 + .pdma_base = PDMA_V1_BASE,
5233 + .txd_size = sizeof(struct mtk_tx_dma),
5234 + .rxd_size = sizeof(struct mtk_rx_dma),
5235 +};
5236 +
5237 +static const struct mtk_soc_data mt7621_data = {
5238 + .caps = MT7621_CAPS,
5239 + .gdma_count = 2,
5240 + .pdma_base = PDMA_V1_BASE,
5241 + .txd_size = sizeof(struct mtk_tx_dma),
5242 + .rxd_size = sizeof(struct mtk_rx_dma),
5243 +};
5244 +
5245 +static const struct udevice_id mtk_eth_ids[] = {
5246 + { .compatible = "mediatek,mt7988-eth", .data = (ulong)&mt7988_data },
5247 + { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
5248 + { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
5249 + { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
5250 + { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data },
5251 + { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data },
5252 + { .compatible = "mediatek,mt7621-eth", .data = (ulong)&mt7621_data },
5253 + {}
5254 +};
5255 +
5256 +static const struct eth_ops mtk_eth_ops = {
5257 + .start = mtk_eth_start,
5258 + .stop = mtk_eth_stop,
5259 + .send = mtk_eth_send,
5260 + .recv = mtk_eth_recv,
5261 + .free_pkt = mtk_eth_free_pkt,
5262 + .write_hwaddr = mtk_eth_write_hwaddr,
5263 +};
5264 +
5265 +U_BOOT_DRIVER(mtk_eth) = {
5266 + .name = "mtk-eth",
5267 + .id = UCLASS_ETH,
5268 + .of_match = mtk_eth_ids,
5269 + .of_to_plat = mtk_eth_of_to_plat,
5270 + .plat_auto = sizeof(struct eth_pdata),
5271 + .probe = mtk_eth_probe,
5272 + .remove = mtk_eth_remove,
5273 + .ops = &mtk_eth_ops,
5274 + .priv_auto = sizeof(struct mtk_eth_priv),
5275 + .flags = DM_FLAG_ALLOC_PRIV_DMA,
5276 +};
5277 --- a/drivers/net/mtk_eth.h
5278 +++ /dev/null
5279 @@ -1,600 +0,0 @@
5280 -/* SPDX-License-Identifier: GPL-2.0 */
5281 -/*
5282 - * Copyright (C) 2018 MediaTek Inc.
5283 - *
5284 - * Author: Weijie Gao <weijie.gao@mediatek.com>
5285 - * Author: Mark Lee <mark-mc.lee@mediatek.com>
5286 - */
5287 -
5288 -#ifndef _MTK_ETH_H_
5289 -#define _MTK_ETH_H_
5290 -
5291 -#include <linux/bitops.h>
5292 -#include <linux/bitfield.h>
5293 -
5294 -enum mkt_eth_capabilities {
5295 - MTK_TRGMII_BIT,
5296 - MTK_TRGMII_MT7621_CLK_BIT,
5297 - MTK_U3_COPHY_V2_BIT,
5298 - MTK_INFRA_BIT,
5299 - MTK_NETSYS_V2_BIT,
5300 - MTK_NETSYS_V3_BIT,
5301 -
5302 - /* PATH BITS */
5303 - MTK_ETH_PATH_GMAC1_TRGMII_BIT,
5304 - MTK_ETH_PATH_GMAC2_SGMII_BIT,
5305 - MTK_ETH_PATH_MT7622_SGMII_BIT,
5306 - MTK_ETH_PATH_MT7629_GMAC2_BIT,
5307 -};
5308 -
5309 -#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
5310 -#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
5311 -#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
5312 -#define MTK_INFRA BIT(MTK_INFRA_BIT)
5313 -#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
5314 -#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT)
5315 -
5316 -/* Supported path present on SoCs */
5317 -#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
5318 -
5319 -#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
5320 -#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT)
5321 -#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT)
5322 -
5323 -#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
5324 -
5325 -#define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA)
5326 -
5327 -#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
5328 -
5329 -#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
5330 -
5331 -#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII)
5332 -
5333 -#define MT7623_CAPS (MTK_GMAC1_TRGMII)
5334 -
5335 -#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA)
5336 -
5337 -#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
5338 -
5339 -#define MT7986_CAPS (MTK_NETSYS_V2)
5340 -
5341 -#define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA)
5342 -
5343 -/* Frame Engine Register Bases */
5344 -#define PDMA_V1_BASE 0x0800
5345 -#define PDMA_V2_BASE 0x6000
5346 -#define PDMA_V3_BASE 0x6800
5347 -#define GDMA1_BASE 0x0500
5348 -#define GDMA2_BASE 0x1500
5349 -#define GDMA3_BASE 0x0540
5350 -#define GMAC_BASE 0x10000
5351 -#define GSW_BASE 0x20000
5352 -
5353 -/* Ethernet subsystem registers */
5354 -
5355 -#define ETHSYS_SYSCFG1_REG 0x14
5356 -#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2))
5357 -#define SYSCFG1_GE_MODE_M 0x3
5358 -#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8)
5359 -#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac))
5360 -
5361 -#define ETHSYS_CLKCFG0_REG 0x2c
5362 -#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
5363 -
5364 -/* Top misc registers */
5365 -#define TOPMISC_NETSYS_PCS_MUX 0x84
5366 -#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
5367 -#define MUX_G2_USXGMII_SEL BIT(1)
5368 -#define MUX_HSGMII1_G1_SEL BIT(0)
5369 -
5370 -#define USB_PHY_SWITCH_REG 0x218
5371 -#define QPHY_SEL_MASK 0x3
5372 -#define SGMII_QPHY_SEL 0x2
5373 -
5374 -#define MT7629_INFRA_MISC2_REG 0x70c
5375 -#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0)
5376 -
5377 -/* SYSCFG1_GE_MODE: GE Modes */
5378 -#define GE_MODE_RGMII 0
5379 -#define GE_MODE_MII 1
5380 -#define GE_MODE_MII_PHY 2
5381 -#define GE_MODE_RMII 3
5382 -
5383 -/* SGMII subsystem config registers */
5384 -#define SGMSYS_PCS_CONTROL_1 0x0
5385 -#define SGMII_LINK_STATUS BIT(18)
5386 -#define SGMII_AN_ENABLE BIT(12)
5387 -#define SGMII_AN_RESTART BIT(9)
5388 -
5389 -#define SGMSYS_SGMII_MODE 0x20
5390 -#define SGMII_AN_MODE 0x31120103
5391 -#define SGMII_FORCE_MODE 0x31120019
5392 -
5393 -#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
5394 -#define SGMII_PHYA_PWD BIT(4)
5395 -
5396 -#define SGMSYS_QPHY_WRAP_CTRL 0xec
5397 -#define SGMII_PN_SWAP_TX_RX 0x03
5398 -
5399 -#define SGMSYS_GEN2_SPEED 0x2028
5400 -#define SGMSYS_GEN2_SPEED_V2 0x128
5401 -#define SGMSYS_SPEED_MASK GENMASK(3, 2)
5402 -#define SGMSYS_SPEED_2500 1
5403 -
5404 -/* USXGMII subsystem config registers */
5405 -/* Register to control USXGMII XFI PLL digital */
5406 -#define XFI_PLL_DIG_GLB8 0x08
5407 -#define RG_XFI_PLL_EN BIT(31)
5408 -
5409 -/* Register to control USXGMII XFI PLL analog */
5410 -#define XFI_PLL_ANA_GLB8 0x108
5411 -#define RG_XFI_PLL_ANA_SWWA 0x02283248
5412 -
5413 -/* Frame Engine Registers */
5414 -#define PSE_NO_DROP_CFG_REG 0x108
5415 -#define PSE_NO_DROP_GDM1 BIT(1)
5416 -
5417 -#define FE_GLO_MISC_REG 0x124
5418 -#define PDMA_VER_V2 BIT(4)
5419 -
5420 -/* PDMA */
5421 -#define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10)
5422 -#define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10)
5423 -#define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10)
5424 -#define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10)
5425 -
5426 -#define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10)
5427 -#define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10)
5428 -#define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10)
5429 -#define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10)
5430 -
5431 -#define PDMA_GLO_CFG_REG 0x204
5432 -#define TX_WB_DDONE BIT(6)
5433 -#define RX_DMA_BUSY BIT(3)
5434 -#define RX_DMA_EN BIT(2)
5435 -#define TX_DMA_BUSY BIT(1)
5436 -#define TX_DMA_EN BIT(0)
5437 -
5438 -#define PDMA_RST_IDX_REG 0x208
5439 -#define RST_DRX_IDX0 BIT(16)
5440 -#define RST_DTX_IDX0 BIT(0)
5441 -
5442 -/* GDMA */
5443 -#define GDMA_IG_CTRL_REG 0x000
5444 -#define GDM_ICS_EN BIT(22)
5445 -#define GDM_TCS_EN BIT(21)
5446 -#define GDM_UCS_EN BIT(20)
5447 -#define STRP_CRC BIT(16)
5448 -#define MYMAC_DP_S 12
5449 -#define MYMAC_DP_M 0xf000
5450 -#define BC_DP_S 8
5451 -#define BC_DP_M 0xf00
5452 -#define MC_DP_S 4
5453 -#define MC_DP_M 0xf0
5454 -#define UN_DP_S 0
5455 -#define UN_DP_M 0x0f
5456 -
5457 -#define GDMA_EG_CTRL_REG 0x004
5458 -#define GDMA_CPU_BRIDGE_EN BIT(31)
5459 -
5460 -#define GDMA_MAC_LSB_REG 0x008
5461 -
5462 -#define GDMA_MAC_MSB_REG 0x00c
5463 -
5464 -/* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */
5465 -#define DP_PDMA 0
5466 -#define DP_GDMA1 1
5467 -#define DP_GDMA2 2
5468 -#define DP_PPE 4
5469 -#define DP_QDMA 5
5470 -#define DP_DISCARD 7
5471 -
5472 -/* GMAC Registers */
5473 -
5474 -#define GMAC_PPSC_REG 0x0000
5475 -#define PHY_MDC_CFG GENMASK(29, 24)
5476 -#define MDC_TURBO BIT(20)
5477 -#define MDC_MAX_FREQ 25000000
5478 -#define MDC_MAX_DIVIDER 63
5479 -
5480 -#define GMAC_PIAC_REG 0x0004
5481 -#define PHY_ACS_ST BIT(31)
5482 -#define MDIO_REG_ADDR_S 25
5483 -#define MDIO_REG_ADDR_M 0x3e000000
5484 -#define MDIO_PHY_ADDR_S 20
5485 -#define MDIO_PHY_ADDR_M 0x1f00000
5486 -#define MDIO_CMD_S 18
5487 -#define MDIO_CMD_M 0xc0000
5488 -#define MDIO_ST_S 16
5489 -#define MDIO_ST_M 0x30000
5490 -#define MDIO_RW_DATA_S 0
5491 -#define MDIO_RW_DATA_M 0xffff
5492 -
5493 -#define GMAC_XGMAC_STS_REG 0x000c
5494 -#define P1_XGMAC_FORCE_LINK BIT(15)
5495 -
5496 -#define GMAC_MAC_MISC_REG 0x0010
5497 -#define MISC_MDC_TURBO BIT(4)
5498 -
5499 -#define GMAC_GSW_CFG_REG 0x0080
5500 -#define GSWTX_IPG_M 0xF0000
5501 -#define GSWTX_IPG_S 16
5502 -#define GSWRX_IPG_M 0xF
5503 -#define GSWRX_IPG_S 0
5504 -
5505 -/* MDIO_CMD: MDIO commands */
5506 -#define MDIO_CMD_ADDR 0
5507 -#define MDIO_CMD_WRITE 1
5508 -#define MDIO_CMD_READ 2
5509 -#define MDIO_CMD_READ_C45 3
5510 -
5511 -/* MDIO_ST: MDIO start field */
5512 -#define MDIO_ST_C45 0
5513 -#define MDIO_ST_C22 1
5514 -
5515 -#define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100)
5516 -#define MAC_RX_PKT_LEN_S 24
5517 -#define MAC_RX_PKT_LEN_M 0x3000000
5518 -#define IPG_CFG_S 18
5519 -#define IPG_CFG_M 0xc0000
5520 -#define MAC_MODE BIT(16)
5521 -#define FORCE_MODE BIT(15)
5522 -#define MAC_TX_EN BIT(14)
5523 -#define MAC_RX_EN BIT(13)
5524 -#define DEL_RXFIFO_CLR BIT(12)
5525 -#define BKOFF_EN BIT(9)
5526 -#define BACKPR_EN BIT(8)
5527 -#define FORCE_RX_FC BIT(5)
5528 -#define FORCE_TX_FC BIT(4)
5529 -#define FORCE_SPD_S 2
5530 -#define FORCE_SPD_M 0x0c
5531 -#define FORCE_DPX BIT(1)
5532 -#define FORCE_LINK BIT(0)
5533 -
5534 -/* Values of IPG_CFG */
5535 -#define IPG_96BIT 0
5536 -#define IPG_96BIT_WITH_SHORT_IPG 1
5537 -#define IPG_64BIT 2
5538 -
5539 -/* MAC_RX_PKT_LEN: Max RX packet length */
5540 -#define MAC_RX_PKT_LEN_1518 0
5541 -#define MAC_RX_PKT_LEN_1536 1
5542 -#define MAC_RX_PKT_LEN_1552 2
5543 -#define MAC_RX_PKT_LEN_JUMBO 3
5544 -
5545 -/* FORCE_SPD: Forced link speed */
5546 -#define SPEED_10M 0
5547 -#define SPEED_100M 1
5548 -#define SPEED_1000M 2
5549 -
5550 -#define GMAC_TRGMII_RCK_CTRL 0x300
5551 -#define RX_RST BIT(31)
5552 -#define RXC_DQSISEL BIT(30)
5553 -
5554 -#define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8)
5555 -#define TD_DM_DRVN_S 4
5556 -#define TD_DM_DRVN_M 0xf0
5557 -#define TD_DM_DRVP_S 0
5558 -#define TD_DM_DRVP_M 0x0f
5559 -
5560 -/* XGMAC Status Registers */
5561 -#define XGMAC_STS(x) (((x) == 2) ? 0x001C : 0x000C)
5562 -#define XGMAC_FORCE_LINK(x) (((x) == 1) ? BIT(31) : BIT(15))
5563 -
5564 -/* XGMAC Registers */
5565 -#define XGMAC_PORT_MCR(x) (0x2000 + (((x) - 1) * 0x1000))
5566 -#define XGMAC_TRX_DISABLE 0xf
5567 -#define XGMAC_FORCE_TX_FC BIT(5)
5568 -#define XGMAC_FORCE_RX_FC BIT(4)
5569 -
5570 -/* MT7530 Registers */
5571 -
5572 -#define PCR_REG(p) (0x2004 + (p) * 0x100)
5573 -#define PORT_MATRIX_S 16
5574 -#define PORT_MATRIX_M 0xff0000
5575 -
5576 -#define PVC_REG(p) (0x2010 + (p) * 0x100)
5577 -#define STAG_VPID_S 16
5578 -#define STAG_VPID_M 0xffff0000
5579 -#define VLAN_ATTR_S 6
5580 -#define VLAN_ATTR_M 0xc0
5581 -
5582 -/* VLAN_ATTR: VLAN attributes */
5583 -#define VLAN_ATTR_USER 0
5584 -#define VLAN_ATTR_STACK 1
5585 -#define VLAN_ATTR_TRANSLATION 2
5586 -#define VLAN_ATTR_TRANSPARENT 3
5587 -
5588 -#define PMCR_REG(p) (0x3000 + (p) * 0x100)
5589 -/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR
5590 - * MT7531 specific fields are defined below
5591 - */
5592 -#define FORCE_MODE_EEE1G BIT(25)
5593 -#define FORCE_MODE_EEE100 BIT(26)
5594 -#define FORCE_MODE_TX_FC BIT(27)
5595 -#define FORCE_MODE_RX_FC BIT(28)
5596 -#define FORCE_MODE_DPX BIT(29)
5597 -#define FORCE_MODE_SPD BIT(30)
5598 -#define FORCE_MODE_LNK BIT(31)
5599 -#define MT7531_FORCE_MODE FORCE_MODE_EEE1G | FORCE_MODE_EEE100 |\
5600 - FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
5601 - FORCE_MODE_DPX | FORCE_MODE_SPD | \
5602 - FORCE_MODE_LNK
5603 -#define MT7988_FORCE_MODE FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
5604 - FORCE_MODE_DPX | FORCE_MODE_SPD | \
5605 - FORCE_MODE_LNK
5606 -
5607 -/* MT7531 SGMII Registers */
5608 -#define MT7531_SGMII_REG_BASE 0x5000
5609 -#define MT7531_SGMII_REG_PORT_BASE 0x1000
5610 -#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
5611 - (p) * MT7531_SGMII_REG_PORT_BASE + (r))
5612 -#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00)
5613 -#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20)
5614 -#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8)
5615 -#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128)
5616 -/* XXX: all fields of MT7531 SGMII are defined under SGMSYS */
5617 -
5618 -/* MT753x System Control Register */
5619 -#define SYS_CTRL_REG 0x7000
5620 -#define SW_PHY_RST BIT(2)
5621 -#define SW_SYS_RST BIT(1)
5622 -#define SW_REG_RST BIT(0)
5623 -
5624 -/* MT7531 */
5625 -#define MT7531_PHY_IAC 0x701c
5626 -/* XXX: all fields are defined under GMAC_PIAC_REG */
5627 -
5628 -#define MT7531_CLKGEN_CTRL 0x7500
5629 -#define CLK_SKEW_OUT_S 8
5630 -#define CLK_SKEW_OUT_M 0x300
5631 -#define CLK_SKEW_IN_S 6
5632 -#define CLK_SKEW_IN_M 0xc0
5633 -#define RXCLK_NO_DELAY BIT(5)
5634 -#define TXCLK_NO_REVERSE BIT(4)
5635 -#define GP_MODE_S 1
5636 -#define GP_MODE_M 0x06
5637 -#define GP_CLK_EN BIT(0)
5638 -
5639 -/* Values of GP_MODE */
5640 -#define GP_MODE_RGMII 0
5641 -#define GP_MODE_MII 1
5642 -#define GP_MODE_REV_MII 2
5643 -
5644 -/* Values of CLK_SKEW_IN */
5645 -#define CLK_SKEW_IN_NO_CHANGE 0
5646 -#define CLK_SKEW_IN_DELAY_100PPS 1
5647 -#define CLK_SKEW_IN_DELAY_200PPS 2
5648 -#define CLK_SKEW_IN_REVERSE 3
5649 -
5650 -/* Values of CLK_SKEW_OUT */
5651 -#define CLK_SKEW_OUT_NO_CHANGE 0
5652 -#define CLK_SKEW_OUT_DELAY_100PPS 1
5653 -#define CLK_SKEW_OUT_DELAY_200PPS 2
5654 -#define CLK_SKEW_OUT_REVERSE 3
5655 -
5656 -#define HWTRAP_REG 0x7800
5657 -/* MT7530 Modified Hardware Trap Status Registers */
5658 -#define MHWTRAP_REG 0x7804
5659 -#define CHG_TRAP BIT(16)
5660 -#define LOOPDET_DIS BIT(14)
5661 -#define P5_INTF_SEL_S 13
5662 -#define P5_INTF_SEL_M 0x2000
5663 -#define SMI_ADDR_S 11
5664 -#define SMI_ADDR_M 0x1800
5665 -#define XTAL_FSEL_S 9
5666 -#define XTAL_FSEL_M 0x600
5667 -#define P6_INTF_DIS BIT(8)
5668 -#define P5_INTF_MODE_S 7
5669 -#define P5_INTF_MODE_M 0x80
5670 -#define P5_INTF_DIS BIT(6)
5671 -#define C_MDIO_BPS BIT(5)
5672 -#define CHIP_MODE_S 0
5673 -#define CHIP_MODE_M 0x0f
5674 -
5675 -/* P5_INTF_SEL: Interface type of Port5 */
5676 -#define P5_INTF_SEL_GPHY 0
5677 -#define P5_INTF_SEL_GMAC5 1
5678 -
5679 -/* P5_INTF_MODE: Interface mode of Port5 */
5680 -#define P5_INTF_MODE_GMII_MII 0
5681 -#define P5_INTF_MODE_RGMII 1
5682 -
5683 -#define MT7530_P6ECR 0x7830
5684 -#define P6_INTF_MODE_M 0x3
5685 -#define P6_INTF_MODE_S 0
5686 -
5687 -/* P6_INTF_MODE: Interface mode of Port6 */
5688 -#define P6_INTF_MODE_RGMII 0
5689 -#define P6_INTF_MODE_TRGMII 1
5690 -
5691 -#define NUM_TRGMII_CTRL 5
5692 -
5693 -#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8)
5694 -#define RD_TAP_S 0
5695 -#define RD_TAP_M 0x7f
5696 -
5697 -#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8)
5698 -/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */
5699 -
5700 -/* TOP Signals Status Register */
5701 -#define MT7531_TOP_SIG_SR 0x780c
5702 -#define PAD_MCM_SMI_EN BIT(0)
5703 -#define PAD_DUAL_SGMII_EN BIT(1)
5704 -
5705 -/* MT7531 PLLGP Registers */
5706 -#define MT7531_PLLGP_EN 0x7820
5707 -#define EN_COREPLL BIT(2)
5708 -#define SW_CLKSW BIT(1)
5709 -#define SW_PLLGP BIT(0)
5710 -
5711 -#define MT7531_PLLGP_CR0 0x78a8
5712 -#define RG_COREPLL_EN BIT(22)
5713 -#define RG_COREPLL_POSDIV_S 23
5714 -#define RG_COREPLL_POSDIV_M 0x3800000
5715 -#define RG_COREPLL_SDM_PCW_S 1
5716 -#define RG_COREPLL_SDM_PCW_M 0x3ffffe
5717 -#define RG_COREPLL_SDM_PCW_CHG BIT(0)
5718 -
5719 -/* MT7531 RGMII and SGMII PLL clock */
5720 -#define MT7531_ANA_PLLGP_CR2 0x78b0
5721 -#define MT7531_ANA_PLLGP_CR5 0x78bc
5722 -
5723 -/* MT7531 GPIO GROUP IOLB SMT0 Control */
5724 -#define MT7531_SMT0_IOLB 0x7f04
5725 -#define SMT_IOLB_5_SMI_MDC_EN BIT(5)
5726 -
5727 -/* MT7530 GPHY MDIO Indirect Access Registers */
5728 -#define MII_MMD_ACC_CTL_REG 0x0d
5729 -#define MMD_CMD_S 14
5730 -#define MMD_CMD_M 0xc000
5731 -#define MMD_DEVAD_S 0
5732 -#define MMD_DEVAD_M 0x1f
5733 -
5734 -/* MMD_CMD: MMD commands */
5735 -#define MMD_ADDR 0
5736 -#define MMD_DATA 1
5737 -#define MMD_DATA_RW_POST_INC 2
5738 -#define MMD_DATA_W_POST_INC 3
5739 -
5740 -#define MII_MMD_ADDR_DATA_REG 0x0e
5741 -
5742 -/* MT7530 GPHY MDIO MMD Registers */
5743 -#define CORE_PLL_GROUP2 0x401
5744 -#define RG_SYSPLL_EN_NORMAL BIT(15)
5745 -#define RG_SYSPLL_VODEN BIT(14)
5746 -#define RG_SYSPLL_POSDIV_S 5
5747 -#define RG_SYSPLL_POSDIV_M 0x60
5748 -
5749 -#define CORE_PLL_GROUP4 0x403
5750 -#define MT7531_BYPASS_MODE BIT(4)
5751 -#define MT7531_POWER_ON_OFF BIT(5)
5752 -#define RG_SYSPLL_DDSFBK_EN BIT(12)
5753 -#define RG_SYSPLL_BIAS_EN BIT(11)
5754 -#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
5755 -
5756 -#define CORE_PLL_GROUP5 0x404
5757 -#define RG_LCDDS_PCW_NCPO1_S 0
5758 -#define RG_LCDDS_PCW_NCPO1_M 0xffff
5759 -
5760 -#define CORE_PLL_GROUP6 0x405
5761 -#define RG_LCDDS_PCW_NCPO0_S 0
5762 -#define RG_LCDDS_PCW_NCPO0_M 0xffff
5763 -
5764 -#define CORE_PLL_GROUP7 0x406
5765 -#define RG_LCDDS_PWDB BIT(15)
5766 -#define RG_LCDDS_ISO_EN BIT(13)
5767 -#define RG_LCCDS_C_S 4
5768 -#define RG_LCCDS_C_M 0x70
5769 -#define RG_LCDDS_PCW_NCPO_CHG BIT(3)
5770 -
5771 -#define CORE_PLL_GROUP10 0x409
5772 -#define RG_LCDDS_SSC_DELTA_S 0
5773 -#define RG_LCDDS_SSC_DELTA_M 0xfff
5774 -
5775 -#define CORE_PLL_GROUP11 0x40a
5776 -#define RG_LCDDS_SSC_DELTA1_S 0
5777 -#define RG_LCDDS_SSC_DELTA1_M 0xfff
5778 -
5779 -#define CORE_GSWPLL_GRP1 0x40d
5780 -#define RG_GSWPLL_POSDIV_200M_S 12
5781 -#define RG_GSWPLL_POSDIV_200M_M 0x3000
5782 -#define RG_GSWPLL_EN_PRE BIT(11)
5783 -#define RG_GSWPLL_FBKDIV_200M_S 0
5784 -#define RG_GSWPLL_FBKDIV_200M_M 0xff
5785 -
5786 -#define CORE_GSWPLL_GRP2 0x40e
5787 -#define RG_GSWPLL_POSDIV_500M_S 8
5788 -#define RG_GSWPLL_POSDIV_500M_M 0x300
5789 -#define RG_GSWPLL_FBKDIV_500M_S 0
5790 -#define RG_GSWPLL_FBKDIV_500M_M 0xff
5791 -
5792 -#define CORE_TRGMII_GSW_CLK_CG 0x410
5793 -#define REG_GSWCK_EN BIT(0)
5794 -#define REG_TRGMIICK_EN BIT(1)
5795 -
5796 -/* Extend PHY Control Register 3 */
5797 -#define PHY_EXT_REG_14 0x14
5798 -
5799 -/* Fields of PHY_EXT_REG_14 */
5800 -#define PHY_EN_DOWN_SHFIT BIT(4)
5801 -
5802 -/* Extend PHY Control Register 4 */
5803 -#define PHY_EXT_REG_17 0x17
5804 -
5805 -/* Fields of PHY_EXT_REG_17 */
5806 -#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4)
5807 -
5808 -/* PHY RXADC Control Register 7 */
5809 -#define PHY_DEV1E_REG_0C6 0x0c6
5810 -
5811 -/* Fields of PHY_DEV1E_REG_0C6 */
5812 -#define PHY_POWER_SAVING_S 8
5813 -#define PHY_POWER_SAVING_M 0x300
5814 -#define PHY_POWER_SAVING_TX 0x0
5815 -
5816 -/* PDMA descriptors */
5817 -struct mtk_rx_dma {
5818 - unsigned int rxd1;
5819 - unsigned int rxd2;
5820 - unsigned int rxd3;
5821 - unsigned int rxd4;
5822 -} __packed __aligned(4);
5823 -
5824 -struct mtk_rx_dma_v2 {
5825 - unsigned int rxd1;
5826 - unsigned int rxd2;
5827 - unsigned int rxd3;
5828 - unsigned int rxd4;
5829 - unsigned int rxd5;
5830 - unsigned int rxd6;
5831 - unsigned int rxd7;
5832 - unsigned int rxd8;
5833 -} __packed __aligned(4);
5834 -
5835 -struct mtk_tx_dma {
5836 - unsigned int txd1;
5837 - unsigned int txd2;
5838 - unsigned int txd3;
5839 - unsigned int txd4;
5840 -} __packed __aligned(4);
5841 -
5842 -struct mtk_tx_dma_v2 {
5843 - unsigned int txd1;
5844 - unsigned int txd2;
5845 - unsigned int txd3;
5846 - unsigned int txd4;
5847 - unsigned int txd5;
5848 - unsigned int txd6;
5849 - unsigned int txd7;
5850 - unsigned int txd8;
5851 -} __packed __aligned(4);
5852 -
5853 -/* PDMA TXD fields */
5854 -#define PDMA_TXD2_DDONE BIT(31)
5855 -#define PDMA_TXD2_LS0 BIT(30)
5856 -#define PDMA_V1_TXD2_SDL0_M GENMASK(29, 16)
5857 -#define PDMA_V1_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V1_TXD2_SDL0_M, (_v))
5858 -#define PDMA_V2_TXD2_SDL0_M GENMASK(23, 8)
5859 -#define PDMA_V2_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V2_TXD2_SDL0_M, (_v))
5860 -
5861 -#define PDMA_V1_TXD4_FPORT_M GENMASK(27, 25)
5862 -#define PDMA_V1_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V1_TXD4_FPORT_M, (_v))
5863 -#define PDMA_V2_TXD4_FPORT_M GENMASK(27, 24)
5864 -#define PDMA_V2_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD4_FPORT_M, (_v))
5865 -
5866 -#define PDMA_V2_TXD5_FPORT_M GENMASK(19, 16)
5867 -#define PDMA_V2_TXD5_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD5_FPORT_M, (_v))
5868 -
5869 -/* PDMA RXD fields */
5870 -#define PDMA_RXD2_DDONE BIT(31)
5871 -#define PDMA_RXD2_LS0 BIT(30)
5872 -#define PDMA_V1_RXD2_PLEN0_M GENMASK(29, 16)
5873 -#define PDMA_V1_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V1_RXD2_PLEN0_M, (_v))
5874 -#define PDMA_V1_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V1_RXD2_PLEN0_M, (_v))
5875 -#define PDMA_V2_RXD2_PLEN0_M GENMASK(23, 8)
5876 -#define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v))
5877 -#define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v))
5878 -
5879 -#endif /* _MTK_ETH_H_ */
5880 --- /dev/null
5881 +++ b/drivers/net/mtk_eth/mtk_eth.h
5882 @@ -0,0 +1,429 @@
5883 +/* SPDX-License-Identifier: GPL-2.0 */
5884 +/*
5885 + * Copyright (C) 2025 MediaTek Inc.
5886 + *
5887 + * Author: Weijie Gao <weijie.gao@mediatek.com>
5888 + * Author: Mark Lee <mark-mc.lee@mediatek.com>
5889 + */
5890 +
5891 +#ifndef _MTK_ETH_H_
5892 +#define _MTK_ETH_H_
5893 +
5894 +#include <linker_lists.h>
5895 +#include <linux/bitops.h>
5896 +#include <linux/bitfield.h>
5897 +
5898 +struct mtk_eth_priv;
5899 +struct mtk_eth_switch_priv;
5900 +
5901 +/* struct mtk_soc_data - This is the structure holding all differences
5902 + * among various plaforms
5903 + * @caps Flags shown the extra capability for the SoC
5904 + * @ana_rgc3: The offset for register ANA_RGC3 related to
5905 + * sgmiisys syscon
5906 + * @gdma_count: Number of GDMAs
5907 + * @pdma_base: Register base of PDMA block
5908 + * @txd_size: Tx DMA descriptor size.
5909 + * @rxd_size: Rx DMA descriptor size.
5910 + */
5911 +struct mtk_soc_data {
5912 + u32 caps;
5913 + u32 ana_rgc3;
5914 + u32 gdma_count;
5915 + u32 pdma_base;
5916 + u32 txd_size;
5917 + u32 rxd_size;
5918 +};
5919 +
5920 +struct mtk_eth_switch {
5921 + const char *name;
5922 + const char *desc;
5923 + size_t priv_size;
5924 + u32 reset_wait_time;
5925 +
5926 + int (*detect)(struct mtk_eth_priv *priv);
5927 + int (*setup)(struct mtk_eth_switch_priv *priv);
5928 + int (*cleanup)(struct mtk_eth_switch_priv *priv);
5929 + void (*mac_control)(struct mtk_eth_switch_priv *priv, bool enable);
5930 +};
5931 +
5932 +#define MTK_ETH_SWITCH(__name) \
5933 + ll_entry_declare(struct mtk_eth_switch, __name, mtk_eth_switch)
5934 +
5935 +struct mtk_eth_switch_priv {
5936 + struct mtk_eth_priv *eth;
5937 + const struct mtk_eth_switch *sw;
5938 + const struct mtk_soc_data *soc;
5939 + void *ethsys_base;
5940 + int phy_interface;
5941 +};
5942 +
5943 +enum mkt_eth_capabilities {
5944 + MTK_TRGMII_BIT,
5945 + MTK_TRGMII_MT7621_CLK_BIT,
5946 + MTK_U3_COPHY_V2_BIT,
5947 + MTK_INFRA_BIT,
5948 + MTK_NETSYS_V2_BIT,
5949 + MTK_NETSYS_V3_BIT,
5950 +
5951 + /* PATH BITS */
5952 + MTK_ETH_PATH_GMAC1_TRGMII_BIT,
5953 + MTK_ETH_PATH_GMAC2_SGMII_BIT,
5954 + MTK_ETH_PATH_MT7622_SGMII_BIT,
5955 + MTK_ETH_PATH_MT7629_GMAC2_BIT,
5956 +};
5957 +
5958 +#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
5959 +#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
5960 +#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
5961 +#define MTK_INFRA BIT(MTK_INFRA_BIT)
5962 +#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
5963 +#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT)
5964 +
5965 +/* Supported path present on SoCs */
5966 +#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
5967 +#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
5968 +#define MTK_ETH_PATH_MT7622_SGMII BIT(MTK_ETH_PATH_MT7622_SGMII_BIT)
5969 +#define MTK_ETH_PATH_MT7629_GMAC2 BIT(MTK_ETH_PATH_MT7629_GMAC2_BIT)
5970 +
5971 +#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
5972 +
5973 +#define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA)
5974 +
5975 +#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
5976 +
5977 +#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
5978 +
5979 +#define MT7622_CAPS (MTK_ETH_PATH_MT7622_SGMII)
5980 +
5981 +#define MT7623_CAPS (MTK_GMAC1_TRGMII)
5982 +
5983 +#define MT7629_CAPS (MTK_ETH_PATH_MT7629_GMAC2 | MTK_INFRA)
5984 +
5985 +#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
5986 +
5987 +#define MT7986_CAPS (MTK_NETSYS_V2)
5988 +
5989 +#define MT7987_CAPS (MTK_NETSYS_V3 | MTK_GMAC2_U3_QPHY | MTK_INFRA)
5990 +
5991 +#define MT7988_CAPS (MTK_NETSYS_V3 | MTK_INFRA)
5992 +
5993 +/* Frame Engine Register Bases */
5994 +#define PDMA_V1_BASE 0x0800
5995 +#define PDMA_V2_BASE 0x6000
5996 +#define PDMA_V3_BASE 0x6800
5997 +#define GDMA1_BASE 0x0500
5998 +#define GDMA2_BASE 0x1500
5999 +#define GDMA3_BASE 0x0540
6000 +#define GMAC_BASE 0x10000
6001 +#define GSW_BASE 0x20000
6002 +
6003 +/* Ethernet subsystem registers */
6004 +#define ETHSYS_SYSCFG1_REG 0x14
6005 +#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2))
6006 +#define SYSCFG1_GE_MODE_M 0x3
6007 +#define SYSCFG1_SGMII_SEL_M GENMASK(9, 8)
6008 +#define SYSCFG1_SGMII_SEL(gmac) BIT(9 - (gmac))
6009 +
6010 +#define ETHSYS_CLKCFG0_REG 0x2c
6011 +#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
6012 +
6013 +/* Top misc registers */
6014 +#define TOPMISC_NETSYS_PCS_MUX 0x84
6015 +#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
6016 +#define MUX_G2_USXGMII_SEL BIT(1)
6017 +#define MUX_HSGMII1_G1_SEL BIT(0)
6018 +
6019 +#define USB_PHY_SWITCH_REG 0x218
6020 +#define QPHY_SEL_MASK 0x3
6021 +#define SGMII_QPHY_SEL 0x2
6022 +
6023 +#define MT7629_INFRA_MISC2_REG 0x70c
6024 +#define INFRA_MISC2_BONDING_OPTION GENMASK(15, 0)
6025 +
6026 +/* SYSCFG1_GE_MODE: GE Modes */
6027 +#define GE_MODE_RGMII 0
6028 +#define GE_MODE_MII 1
6029 +#define GE_MODE_MII_PHY 2
6030 +#define GE_MODE_RMII 3
6031 +
6032 +/* SGMII subsystem config registers */
6033 +#define SGMSYS_PCS_CONTROL_1 0x0
6034 +#define SGMII_LINK_STATUS BIT(18)
6035 +#define SGMII_AN_ENABLE BIT(12)
6036 +#define SGMII_AN_RESTART BIT(9)
6037 +
6038 +#define SGMSYS_SGMII_MODE 0x20
6039 +#define SGMII_AN_MODE 0x31120103
6040 +#define SGMII_FORCE_MODE 0x31120019
6041 +
6042 +#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
6043 +#define SGMII_PHYA_PWD BIT(4)
6044 +
6045 +#define SGMSYS_QPHY_WRAP_CTRL 0xec
6046 +#define SGMII_PN_SWAP_TX_RX 0x03
6047 +
6048 +#define SGMSYS_GEN2_SPEED 0x2028
6049 +#define SGMSYS_GEN2_SPEED_V2 0x128
6050 +#define SGMSYS_SPEED_MASK GENMASK(3, 2)
6051 +#define SGMSYS_SPEED_2500 1
6052 +
6053 +/* USXGMII subsystem config registers */
6054 +/* Register to control USXGMII XFI PLL digital */
6055 +#define XFI_PLL_DIG_GLB8 0x08
6056 +#define RG_XFI_PLL_EN BIT(31)
6057 +
6058 +/* Register to control USXGMII XFI PLL analog */
6059 +#define XFI_PLL_ANA_GLB8 0x108
6060 +#define RG_XFI_PLL_ANA_SWWA 0x02283248
6061 +
6062 +/* Frame Engine Registers */
6063 +#define PSE_NO_DROP_CFG_REG 0x108
6064 +#define PSE_NO_DROP_GDM1 BIT(1)
6065 +
6066 +#define FE_GLO_MISC_REG 0x124
6067 +#define PDMA_VER_V2 BIT(4)
6068 +
6069 +/* PDMA */
6070 +#define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10)
6071 +#define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10)
6072 +#define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10)
6073 +#define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10)
6074 +
6075 +#define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10)
6076 +#define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10)
6077 +#define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10)
6078 +#define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10)
6079 +
6080 +#define PDMA_GLO_CFG_REG 0x204
6081 +#define TX_WB_DDONE BIT(6)
6082 +#define RX_DMA_BUSY BIT(3)
6083 +#define RX_DMA_EN BIT(2)
6084 +#define TX_DMA_BUSY BIT(1)
6085 +#define TX_DMA_EN BIT(0)
6086 +
6087 +#define PDMA_RST_IDX_REG 0x208
6088 +#define RST_DRX_IDX0 BIT(16)
6089 +#define RST_DTX_IDX0 BIT(0)
6090 +
6091 +/* GDMA */
6092 +#define GDMA_IG_CTRL_REG 0x000
6093 +#define GDM_ICS_EN BIT(22)
6094 +#define GDM_TCS_EN BIT(21)
6095 +#define GDM_UCS_EN BIT(20)
6096 +#define STRP_CRC BIT(16)
6097 +#define MYMAC_DP_S 12
6098 +#define MYMAC_DP_M 0xf000
6099 +#define BC_DP_S 8
6100 +#define BC_DP_M 0xf00
6101 +#define MC_DP_S 4
6102 +#define MC_DP_M 0xf0
6103 +#define UN_DP_S 0
6104 +#define UN_DP_M 0x0f
6105 +
6106 +#define GDMA_EG_CTRL_REG 0x004
6107 +#define GDMA_CPU_BRIDGE_EN BIT(31)
6108 +
6109 +#define GDMA_MAC_LSB_REG 0x008
6110 +
6111 +#define GDMA_MAC_MSB_REG 0x00c
6112 +
6113 +/* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */
6114 +#define DP_PDMA 0
6115 +#define DP_GDMA1 1
6116 +#define DP_GDMA2 2
6117 +#define DP_PPE 4
6118 +#define DP_QDMA 5
6119 +#define DP_DISCARD 7
6120 +
6121 +/* GMAC Registers */
6122 +#define GMAC_PPSC_REG 0x0000
6123 +#define PHY_MDC_CFG GENMASK(29, 24)
6124 +#define MDC_TURBO BIT(20)
6125 +#define MDC_MAX_FREQ 25000000
6126 +#define MDC_MAX_DIVIDER 63
6127 +
6128 +#define GMAC_PIAC_REG 0x0004
6129 +#define PHY_ACS_ST BIT(31)
6130 +#define MDIO_REG_ADDR_S 25
6131 +#define MDIO_REG_ADDR_M 0x3e000000
6132 +#define MDIO_PHY_ADDR_S 20
6133 +#define MDIO_PHY_ADDR_M 0x1f00000
6134 +#define MDIO_CMD_S 18
6135 +#define MDIO_CMD_M 0xc0000
6136 +#define MDIO_ST_S 16
6137 +#define MDIO_ST_M 0x30000
6138 +#define MDIO_RW_DATA_S 0
6139 +#define MDIO_RW_DATA_M 0xffff
6140 +
6141 +#define GMAC_XGMAC_STS_REG 0x000c
6142 +#define P1_XGMAC_FORCE_LINK BIT(15)
6143 +
6144 +#define GMAC_MAC_MISC_REG 0x0010
6145 +#define MISC_MDC_TURBO BIT(4)
6146 +
6147 +#define GMAC_GSW_CFG_REG 0x0080
6148 +#define GSWTX_IPG_M 0xF0000
6149 +#define GSWTX_IPG_S 16
6150 +#define GSWRX_IPG_M 0xF
6151 +#define GSWRX_IPG_S 0
6152 +
6153 +/* MDIO_CMD: MDIO commands */
6154 +#define MDIO_CMD_ADDR 0
6155 +#define MDIO_CMD_WRITE 1
6156 +#define MDIO_CMD_READ 2
6157 +#define MDIO_CMD_READ_C45 3
6158 +
6159 +/* MDIO_ST: MDIO start field */
6160 +#define MDIO_ST_C45 0
6161 +#define MDIO_ST_C22 1
6162 +
6163 +#define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100)
6164 +#define MAC_RX_PKT_LEN_S 24
6165 +#define MAC_RX_PKT_LEN_M 0x3000000
6166 +#define IPG_CFG_S 18
6167 +#define IPG_CFG_M 0xc0000
6168 +#define MAC_MODE BIT(16)
6169 +#define FORCE_MODE BIT(15)
6170 +#define MAC_TX_EN BIT(14)
6171 +#define MAC_RX_EN BIT(13)
6172 +#define DEL_RXFIFO_CLR BIT(12)
6173 +#define BKOFF_EN BIT(9)
6174 +#define BACKPR_EN BIT(8)
6175 +#define FORCE_RX_FC BIT(5)
6176 +#define FORCE_TX_FC BIT(4)
6177 +#define FORCE_SPD_S 2
6178 +#define FORCE_SPD_M 0x0c
6179 +#define FORCE_DPX BIT(1)
6180 +#define FORCE_LINK BIT(0)
6181 +
6182 +/* Values of IPG_CFG */
6183 +#define IPG_96BIT 0
6184 +#define IPG_96BIT_WITH_SHORT_IPG 1
6185 +#define IPG_64BIT 2
6186 +
6187 +/* MAC_RX_PKT_LEN: Max RX packet length */
6188 +#define MAC_RX_PKT_LEN_1518 0
6189 +#define MAC_RX_PKT_LEN_1536 1
6190 +#define MAC_RX_PKT_LEN_1552 2
6191 +#define MAC_RX_PKT_LEN_JUMBO 3
6192 +
6193 +/* FORCE_SPD: Forced link speed */
6194 +#define SPEED_10M 0
6195 +#define SPEED_100M 1
6196 +#define SPEED_1000M 2
6197 +
6198 +#define GMAC_TRGMII_RCK_CTRL 0x300
6199 +#define RX_RST BIT(31)
6200 +#define RXC_DQSISEL BIT(30)
6201 +
6202 +#define NUM_TRGMII_CTRL 5
6203 +
6204 +#define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8)
6205 +#define TD_DM_DRVN_S 4
6206 +#define TD_DM_DRVN_M 0xf0
6207 +#define TD_DM_DRVP_S 0
6208 +#define TD_DM_DRVP_M 0x0f
6209 +
6210 +/* XGMAC Status Registers */
6211 +#define XGMAC_STS(x) (((x) == 2) ? 0x001C : 0x000C)
6212 +#define XGMAC_FORCE_LINK(x) (((x) == 1) ? BIT(31) : BIT(15))
6213 +
6214 +/* XGMAC Registers */
6215 +#define XGMAC_PORT_MCR(x) (0x2000 + (((x) - 1) * 0x1000))
6216 +#define XGMAC_TRX_DISABLE 0xf
6217 +#define XGMAC_FORCE_TX_FC BIT(5)
6218 +#define XGMAC_FORCE_RX_FC BIT(4)
6219 +
6220 +/* MDIO Indirect Access Registers */
6221 +#define MII_MMD_ACC_CTL_REG 0x0d
6222 +#define MMD_CMD_S 14
6223 +#define MMD_CMD_M 0xc000
6224 +#define MMD_DEVAD_S 0
6225 +#define MMD_DEVAD_M 0x1f
6226 +
6227 +/* MMD_CMD: MMD commands */
6228 +#define MMD_ADDR 0
6229 +#define MMD_DATA 1
6230 +#define MMD_DATA_RW_POST_INC 2
6231 +#define MMD_DATA_W_POST_INC 3
6232 +
6233 +#define MII_MMD_ADDR_DATA_REG 0x0e
6234 +
6235 +/* PDMA descriptors */
6236 +struct mtk_rx_dma {
6237 + unsigned int rxd1;
6238 + unsigned int rxd2;
6239 + unsigned int rxd3;
6240 + unsigned int rxd4;
6241 +} __packed __aligned(4);
6242 +
6243 +struct mtk_rx_dma_v2 {
6244 + unsigned int rxd1;
6245 + unsigned int rxd2;
6246 + unsigned int rxd3;
6247 + unsigned int rxd4;
6248 + unsigned int rxd5;
6249 + unsigned int rxd6;
6250 + unsigned int rxd7;
6251 + unsigned int rxd8;
6252 +} __packed __aligned(4);
6253 +
6254 +struct mtk_tx_dma {
6255 + unsigned int txd1;
6256 + unsigned int txd2;
6257 + unsigned int txd3;
6258 + unsigned int txd4;
6259 +} __packed __aligned(4);
6260 +
6261 +struct mtk_tx_dma_v2 {
6262 + unsigned int txd1;
6263 + unsigned int txd2;
6264 + unsigned int txd3;
6265 + unsigned int txd4;
6266 + unsigned int txd5;
6267 + unsigned int txd6;
6268 + unsigned int txd7;
6269 + unsigned int txd8;
6270 +} __packed __aligned(4);
6271 +
6272 +/* PDMA TXD fields */
6273 +#define PDMA_TXD2_DDONE BIT(31)
6274 +#define PDMA_TXD2_LS0 BIT(30)
6275 +#define PDMA_V1_TXD2_SDL0_M GENMASK(29, 16)
6276 +#define PDMA_V1_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V1_TXD2_SDL0_M, (_v))
6277 +#define PDMA_V2_TXD2_SDL0_M GENMASK(23, 8)
6278 +#define PDMA_V2_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V2_TXD2_SDL0_M, (_v))
6279 +
6280 +#define PDMA_V1_TXD4_FPORT_M GENMASK(27, 25)
6281 +#define PDMA_V1_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V1_TXD4_FPORT_M, (_v))
6282 +#define PDMA_V2_TXD4_FPORT_M GENMASK(27, 24)
6283 +#define PDMA_V2_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD4_FPORT_M, (_v))
6284 +
6285 +#define PDMA_V2_TXD5_FPORT_M GENMASK(19, 16)
6286 +#define PDMA_V2_TXD5_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD5_FPORT_M, (_v))
6287 +
6288 +/* PDMA RXD fields */
6289 +#define PDMA_RXD2_DDONE BIT(31)
6290 +#define PDMA_RXD2_LS0 BIT(30)
6291 +#define PDMA_V1_RXD2_PLEN0_M GENMASK(29, 16)
6292 +#define PDMA_V1_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V1_RXD2_PLEN0_M, (_v))
6293 +#define PDMA_V1_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V1_RXD2_PLEN0_M, (_v))
6294 +#define PDMA_V2_RXD2_PLEN0_M GENMASK(23, 8)
6295 +#define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v))
6296 +#define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v))
6297 +
6298 +void mtk_fe_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set);
6299 +void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set);
6300 +void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set);
6301 +
6302 +int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg);
6303 +int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data);
6304 +int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg);
6305 +int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
6306 + u16 val);
6307 +int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg);
6308 +int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
6309 + u16 val);
6310 +
6311 +#endif /* _MTK_ETH_H_ */
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