a2e5c4fdd96d8485893bcbf0c1713346ffbb8614
[openwrt/staging/stintel.git] /
1 From 1f3e7ff4f296af1f4350f457d5bd82bc825e645a Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Tue, 1 Oct 2024 12:10:24 +0200
4 Subject: [PATCH 1/2] net: airoha: read default PSE reserved pages value before
5 updating
6
7 Store the default value for the number of PSE reserved pages in orig_val
8 at the beginning of airoha_fe_set_pse_oq_rsv routine, before updating it
9 with airoha_fe_set_pse_queue_rsv_pages().
10 Introduce airoha_fe_get_pse_all_rsv utility routine.
11
12 Introduced by commit 23020f049327 ("net: airoha: Introduce ethernet support
13 for EN7581 SoC")
14
15 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
16 Reviewed-by: Simon Horman <horms@kernel.org>
17 Link: https://patch.msgid.link/20241001-airoha-eth-pse-fix-v2-1-9a56cdffd074@kernel.org
18 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
19 ---
20 drivers/net/ethernet/mediatek/airoha_eth.c | 14 ++++++++++----
21 1 file changed, 10 insertions(+), 4 deletions(-)
22
23 --- a/drivers/net/ethernet/mediatek/airoha_eth.c
24 +++ b/drivers/net/ethernet/mediatek/airoha_eth.c
25 @@ -1116,17 +1116,23 @@ static void airoha_fe_set_pse_queue_rsv_
26 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK);
27 }
28
29 +static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth)
30 +{
31 + u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET);
32 +
33 + return FIELD_GET(PSE_ALLRSV_MASK, val);
34 +}
35 +
36 static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth,
37 u32 port, u32 queue, u32 val)
38 {
39 - u32 orig_val, tmp, all_rsv, fq_limit;
40 + u32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue);
41 + u32 tmp, all_rsv, fq_limit;
42
43 airoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val);
44
45 /* modify all rsv */
46 - orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue);
47 - tmp = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET);
48 - all_rsv = FIELD_GET(PSE_ALLRSV_MASK, tmp);
49 + all_rsv = airoha_fe_get_pse_all_rsv(eth);
50 all_rsv += (val - orig_val);
51 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK,
52 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv));