git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From eb4262203d7d85eb7b6f2696816db272e41f5464 Mon Sep 17 00:00:00 2001
   2 From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
   3 Date: Tue, 4 Feb 2025 14:40:08 +0200
   4 Subject: arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on
   5  RK3588
   6
   7 VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
   8 more accurate pixel clock source to improve handling of display modes up
   9 to 4K@60Hz on video ports 0, 1 and 2.
  10
  11 For now only HDMI0 output is supported, hence add the related PLL clock.
  12
  13 Tested-by: FUKAUMI Naoki <naoki@radxa.com>
  14 Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
  15 Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com
  16 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  17
  18 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
  19 +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
  20 @@ -1261,14 +1261,16 @@
  21                          <&cru DCLK_VOP1>,
  22                          <&cru DCLK_VOP2>,
  23                          <&cru DCLK_VOP3>,
  24 -                        <&cru PCLK_VOP_ROOT>;
  25 +                        <&cru PCLK_VOP_ROOT>,
  26 +                        <&hdptxphy_hdmi0>;
  27                 clock-names = "aclk",
  28                               "hclk",
  29                               "dclk_vp0",
  30                               "dclk_vp1",
  31                               "dclk_vp2",
  32                               "dclk_vp3",
  33 -                             "pclk_vop";
  34 +                             "pclk_vop",
  35 +                             "pll_hdmiphy0";
  36                 iommus = <&vop_mmu>;
  37                 power-domains = <&power RK3588_PD_VOP>;
  38                 rockchip,grf = <&sys_grf>;