git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 0e7a622da17da0042294860cdb7a2fac091d25b1 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Wed, 8 Jan 2025 10:50:40 +0100
   4 Subject: [PATCH 1/6] PCI: mediatek-gen3: Rely on clk_bulk_prepare_enable() in
   5  mtk_pcie_en7581_power_up()
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 Replace clk_bulk_prepare() and clk_bulk_enable() with
  11 clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine.
  12
  13 Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-1-21ac939a3b9b@kernel.org
  14 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  15 Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
  16 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  17 Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  18 ---
  19  drivers/pci/controller/pcie-mediatek-gen3.c | 14 +++-----------
  20  1 file changed, 3 insertions(+), 11 deletions(-)
  21
  22 --- a/drivers/pci/controller/pcie-mediatek-gen3.c
  23 +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
  24 @@ -907,12 +907,6 @@ static int mtk_pcie_en7581_power_up(stru
  25         pm_runtime_enable(dev);
  26         pm_runtime_get_sync(dev);
  27
  28 -       err = clk_bulk_prepare(pcie->num_clks, pcie->clks);
  29 -       if (err) {
  30 -               dev_err(dev, "failed to prepare clock\n");
  31 -               goto err_clk_prepare;
  32 -       }
  33 -
  34         val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) |
  35               FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) |
  36               FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) |
  37 @@ -925,17 +919,15 @@ static int mtk_pcie_en7581_power_up(stru
  38               FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf);
  39         writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG);
  40
  41 -       err = clk_bulk_enable(pcie->num_clks, pcie->clks);
  42 +       err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
  43         if (err) {
  44                 dev_err(dev, "failed to prepare clock\n");
  45 -               goto err_clk_enable;
  46 +               goto err_clk_prepare_enable;
  47         }
  48
  49         return 0;
  50
  51 -err_clk_enable:
  52 -       clk_bulk_unprepare(pcie->num_clks, pcie->clks);
  53 -err_clk_prepare:
  54 +err_clk_prepare_enable:
  55         pm_runtime_put_sync(dev);
  56         pm_runtime_disable(dev);
  57         reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);