git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From edf8afeecfbb0b8c1a2edb8c8892d2f759d35321 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Thu, 19 Jun 2025 09:07:24 +0200
   4 Subject: [PATCH 1/2] net: airoha: Compute number of descriptors according to
   5  reserved memory size
   6
   7 In order to not exceed the reserved memory size for hwfd buffers,
   8 compute the number of hwfd buffers/descriptors according to the
   9 reserved memory size and the size of each hwfd buffer (2KB).
  10
  11 Fixes: 3a1ce9e3d01b ("net: airoha: Add the capability to allocate hwfd buffers via reserved-memory")
  12 Reviewed-by: Simon Horman <horms@kernel.org>
  13 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  14 Link: https://patch.msgid.link/20250619-airoha-hw-num-desc-v4-1-49600a9b319a@kernel.org
  15 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  16 ---
  17  drivers/net/ethernet/airoha/airoha_eth.c | 21 ++++++++++++---------
  18  1 file changed, 12 insertions(+), 9 deletions(-)
  19
  20 --- a/drivers/net/ethernet/airoha/airoha_eth.c
  21 +++ b/drivers/net/ethernet/airoha/airoha_eth.c
  22 @@ -1066,19 +1066,13 @@ static void airoha_qdma_cleanup_tx_queue
  23
  24  static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma)
  25  {
  26 +       int size, index, num_desc = HW_DSCP_NUM;
  27         struct airoha_eth *eth = qdma->eth;
  28         int id = qdma - &eth->qdma[0];
  29         dma_addr_t dma_addr;
  30         const char *name;
  31 -       int size, index;
  32         u32 status;
  33
  34 -       size = HW_DSCP_NUM * sizeof(struct airoha_qdma_fwd_desc);
  35 -       if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))
  36 -               return -ENOMEM;
  37 -
  38 -       airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
  39 -
  40         name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id);
  41         if (!name)
  42                 return -ENOMEM;
  43 @@ -1100,8 +1094,12 @@ static int airoha_qdma_init_hfwd_queues(
  44                 rmem = of_reserved_mem_lookup(np);
  45                 of_node_put(np);
  46                 dma_addr = rmem->base;
  47 +               /* Compute the number of hw descriptors according to the
  48 +                * reserved memory size and the payload buffer size
  49 +                */
  50 +               num_desc = rmem->size / AIROHA_MAX_PACKET_SIZE;
  51         } else {
  52 -               size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM;
  53 +               size = AIROHA_MAX_PACKET_SIZE * num_desc;
  54                 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr,
  55                                          GFP_KERNEL))
  56                         return -ENOMEM;
  57 @@ -1109,6 +1107,11 @@ static int airoha_qdma_init_hfwd_queues(
  58
  59         airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr);
  60
  61 +       size = num_desc * sizeof(struct airoha_qdma_fwd_desc);
  62 +       if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL))
  63 +               return -ENOMEM;
  64 +
  65 +       airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr);
  66         airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG,
  67                         HW_FWD_DSCP_PAYLOAD_SIZE_MASK,
  68                         FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 0));
  69 @@ -1117,7 +1120,7 @@ static int airoha_qdma_init_hfwd_queues(
  70         airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG,
  71                         LMGR_INIT_START | LMGR_SRAM_MODE_MASK |
  72                         HW_FWD_DESC_NUM_MASK,
  73 -                       FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) |
  74 +                       FIELD_PREP(HW_FWD_DESC_NUM_MASK, num_desc) |
  75                         LMGR_INIT_START | LMGR_SRAM_MODE_MASK);
  76
  77         return read_poll_timeout(airoha_qdma_rr, status,