9c9e643ff944f240930e3b571ed9d4dc2a4f2458
[openwrt/staging/pepe2k.git] /
1 From 2d81e1bb625238d40a686ed909ff3e1abab7556a Mon Sep 17 00:00:00 2001
2 From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
3 Date: Mon, 17 Feb 2025 01:16:32 +0300
4 Subject: [PATCH] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround
5
6 Rockchip RK3566/RK3568 GIC600 integration has DDR addressing
7 limited to the first 32bit of physical address space. Rockchip
8 assigned Erratum ID #3568002 for this issue. Add driver quirk for
9 this Rockchip GIC Erratum.
10
11 Note, that the 0x0201743b GIC600 ID is not Rockchip-specific and is
12 common for many ARM GICv3 implementations. Hence, there is an extra
13 of_machine_is_compatible() check.
14
15 Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
16 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
17 Acked-by: Marc Zyngier <maz@kernel.org>
18 Link: https://lore.kernel.org/all/20250216221634.364158-2-dmitry.osipenko@collabora.com
19 ---
20 Documentation/arch/arm64/silicon-errata.rst | 2 ++
21 arch/arm64/Kconfig | 9 ++++++++
22 drivers/irqchip/irq-gic-v3-its.c | 23 ++++++++++++++++++++-
23 3 files changed, 33 insertions(+), 1 deletion(-)
24
25 --- a/Documentation/arch/arm64/silicon-errata.rst
26 +++ b/Documentation/arch/arm64/silicon-errata.rst
27 @@ -270,6 +270,8 @@ stable kernels.
28 +----------------+-----------------+-----------------+-----------------------------+
29 | Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 |
30 +----------------+-----------------+-----------------+-----------------------------+
31 +| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_3568002 |
32 ++----------------+-----------------+-----------------+-----------------------------+
33
34 +----------------+-----------------+-----------------+-----------------------------+
35 | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
36 --- a/arch/arm64/Kconfig
37 +++ b/arch/arm64/Kconfig
38 @@ -1267,6 +1267,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM
39
40 If unsure, say Y.
41
42 +config ROCKCHIP_ERRATUM_3568002
43 + bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB"
44 + default y
45 + help
46 + The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI
47 + addressing limited to the first 32bit of physical address space.
48 +
49 + If unsure, say Y.
50 +
51 config ROCKCHIP_ERRATUM_3588001
52 bool "Rockchip 3588001: GIC600 can not support shareability attributes"
53 default y
54 --- a/drivers/irqchip/irq-gic-v3-its.c
55 +++ b/drivers/irqchip/irq-gic-v3-its.c
56 @@ -202,13 +202,15 @@ static DEFINE_IDA(its_vpeid_ida);
57 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
58 #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
59
60 +static gfp_t gfp_flags_quirk;
61 +
62 static struct page *its_alloc_pages_node(int node, gfp_t gfp,
63 unsigned int order)
64 {
65 struct page *page;
66 int ret = 0;
67
68 - page = alloc_pages_node(node, gfp, order);
69 + page = alloc_pages_node(node, gfp | gfp_flags_quirk, order);
70
71 if (!page)
72 return NULL;
73 @@ -4851,6 +4853,17 @@ static bool its_set_non_coherent(void *d
74 return true;
75 }
76
77 +static bool __maybe_unused its_enable_rk3568002(void *data)
78 +{
79 + if (!of_machine_is_compatible("rockchip,rk3566") &&
80 + !of_machine_is_compatible("rockchip,rk3568"))
81 + return false;
82 +
83 + gfp_flags_quirk |= GFP_DMA32;
84 +
85 + return true;
86 +}
87 +
88 static const struct gic_quirk its_quirks[] = {
89 #ifdef CONFIG_CAVIUM_ERRATUM_22375
90 {
91 @@ -4910,6 +4923,14 @@ static const struct gic_quirk its_quirks
92 .property = "dma-noncoherent",
93 .init = its_set_non_coherent,
94 },
95 +#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002
96 + {
97 + .desc = "ITS: Rockchip erratum RK3568002",
98 + .iidr = 0x0201743b,
99 + .mask = 0xffffffff,
100 + .init = its_enable_rk3568002,
101 + },
102 +#endif
103 {
104 }
105 };